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authorFernando Sahmkow <fsahmkow27@gmail.com>2022-01-30 10:31:13 +0100
committerFernando Sahmkow <fsahmkow27@gmail.com>2022-10-06 21:00:52 +0200
commit668e80a9f42fb4ce0e16f6381d05bcbd286b2da1 (patch)
treea1c668d6c3d00eade849b1d31dba4116095e4c12 /src/video_core/host1x/vic.h
parentTexture Cache: Fix GC and GPU Modified on Joins. (diff)
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Diffstat (limited to 'src/video_core/host1x/vic.h')
-rw-r--r--src/video_core/host1x/vic.h66
1 files changed, 66 insertions, 0 deletions
diff --git a/src/video_core/host1x/vic.h b/src/video_core/host1x/vic.h
new file mode 100644
index 000000000..c51f8af7e
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+++ b/src/video_core/host1x/vic.h
@@ -0,0 +1,66 @@
+// SPDX-FileCopyrightText: Copyright 2020 yuzu Emulator Project
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+#pragma once
+
+#include <memory>
+#include <vector>
+#include "common/common_types.h"
+
+struct SwsContext;
+
+namespace Tegra {
+class GPU;
+
+namespace Host1x {
+
+class Nvdec;
+union VicConfig;
+
+class Vic {
+public:
+ enum class Method : u32 {
+ Execute = 0xc0,
+ SetControlParams = 0x1c1,
+ SetConfigStructOffset = 0x1c2,
+ SetOutputSurfaceLumaOffset = 0x1c8,
+ SetOutputSurfaceChromaOffset = 0x1c9,
+ SetOutputSurfaceChromaUnusedOffset = 0x1ca
+ };
+
+ explicit Vic(GPU& gpu, std::shared_ptr<Nvdec> nvdec_processor);
+
+ ~Vic();
+
+ /// Write to the device state.
+ void ProcessMethod(Method method, u32 argument);
+
+private:
+ void Execute();
+
+ void WriteRGBFrame(const AVFrame* frame, const VicConfig& config);
+
+ void WriteYUVFrame(const AVFrame* frame, const VicConfig& config);
+
+ GPU& gpu;
+ std::shared_ptr<Tegra::Host1x::Nvdec> nvdec_processor;
+
+ /// Avoid reallocation of the following buffers every frame, as their
+ /// size does not change during a stream
+ using AVMallocPtr = std::unique_ptr<u8, decltype(&av_free)>;
+ AVMallocPtr converted_frame_buffer;
+ std::vector<u8> luma_buffer;
+ std::vector<u8> chroma_buffer;
+
+ GPUVAddr config_struct_address{};
+ GPUVAddr output_surface_luma_address{};
+ GPUVAddr output_surface_chroma_address{};
+
+ SwsContext* scaler_ctx{};
+ s32 scaler_width{};
+ s32 scaler_height{};
+};
+
+} // namespace Host1x
+
+} // namespace Tegra