summaryrefslogtreecommitdiffstats
path: root/src/core/arm/interpreter/mmu/cache.cpp
blob: cfbc31f1ed768fdad1ac5b1432d09b658b217166 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
#include "core/arm/skyeye_common/armdefs.h"

/* mmu cache init
 *
 * @cache_t :cache_t to init
 * @width	:cache line width in byte
 * @way		:way of each cache set
 * @set		:cache set num
 *
 * $ -1: error
 * 	 0: sucess
 */
int
mmu_cache_init (cache_s * cache_t, int width, int way, int set, int w_mode)
{
	int i, j;
	cache_set_t *sets;
	cache_line_t *lines;

	/*alloc cache set */
	sets = NULL;
	lines = NULL;
	//fprintf(stderr, "mmu_cache_init: mallloc beg size %d,sets 0x%x\n", sizeof(cache_set_t) * set,sets);
	//exit(-1);
	sets = (cache_set_t *) malloc (sizeof (cache_set_t) * set);
	if (sets == NULL) {
		ERROR_LOG(ARM11, "set malloc size %d\n", sizeof (cache_set_t) * set);
		goto sets_error;
	}
	//fprintf(stderr, "mmu_cache_init: mallloc end sets 0x%x\n", sets);
	cache_t->sets = sets;

	/*init cache set */
	for (i = 0; i < set; i++) {
		/*alloc cache line */
		lines = (cache_line_t *) malloc (sizeof (cache_line_t) * way);
		if (lines == NULL) {
			ERROR_LOG(ARM11, "line malloc size %d\n",
				 sizeof (cache_line_t) * way);
			goto lines_error;
		}
		/*init cache line */
		for (j = 0; j < way; j++) {
			lines[j].tag = 0;	//invalid
			lines[j].data = (ARMword *) malloc (width);
			if (lines[j].data == NULL) {
				ERROR_LOG(ARM11, "data alloc size %d\n", width);
				goto data_error;
			}
		}

		sets[i].lines = lines;
		sets[i].cycle = 0;

	}
	cache_t->width = width;
	cache_t->set = set;
	cache_t->way = way;
	cache_t->w_mode = w_mode;
	return 0;

      data_error:
	/*free data */
	while (j-- > 0)
		free (lines[j].data);
	/*free data error line */
	free (lines);
      lines_error:
	/*free lines already alloced */
	while (i-- > 0) {
		for (j = 0; j < way; j++)
			free (sets[i].lines[j].data);
		free (sets[i].lines);
	}
	/*free sets */
	free (sets);
      sets_error:
	return -1;
};

/* free a cache_t's inner data, the ptr self is not freed,
 * when needed do like below:
 * 		mmu_cache_exit(cache);
 * 		free(cache_t);
 *
 * @cache_t : the cache_t to free
 */

void
mmu_cache_exit (cache_s * cache_t)
{
	int i, j;
	cache_set_t *sets, *set;
	cache_line_t *lines, *line;

	/*free all set */
	sets = cache_t->sets;
	for (set = sets, i = 0; i < cache_t->set; i++, set++) {
		/*free all line */
		lines = set->lines;
		for (line = lines, j = 0; j < cache_t->way; j++, line++)
			free (line->data);
		free (lines);
	}
	free (sets);
}

/* mmu cache search
 *
 * @state	:ARMul_State
 * @cache_t	:cache_t to search
 * @va		:virtual address
 *
 * $	NULL:	no cache match
 * 		cache	:cache matched
 */
cache_line_t *
mmu_cache_search (ARMul_State * state, cache_s * cache_t, ARMword va)
{
	int i;
	int set = va_cache_set (va, cache_t);
	ARMword tag = va_cache_align (va, cache_t);
	cache_line_t *cache;

	cache_set_t *cache_set = cache_t->sets + set;
	for (i = 0, cache = cache_set->lines; i < cache_t->way; i++, cache++) {
		if ((cache->tag & TAG_VALID_FLAG)
		    && (tag == va_cache_align (cache->tag, cache_t)))
			return cache;
	}
	return NULL;
}

/* mmu cache search by set/index
 *
 * @state	:ARMul_State
 * @cache_t	:cache_t to search
 * @index	:set/index value. 
 *
 * $	NULL:	no cache match
 * 		cache	:cache matched
 */
cache_line_t *
mmu_cache_search_by_index (ARMul_State * state, cache_s * cache_t,
			   ARMword index)
{
	int way = cache_t->way;
	int set_v = index_cache_set (index, cache_t);
	int i = 0, index_v = 0;
	cache_set_t *set;

	while ((way >>= 1) >= 1)
		i++;
	index_v = index >> (32 - i);
	set = cache_t->sets + set_v;

	return set->lines + index_v;
}


/* mmu cache alloc
 *
 * @state :ARMul_State
 * @cache_t	:cache_t to alloc from
 * @va		:virtual address that require cache alloc, need not cache aligned
 * @pa		:physical address of va
 *
 * $	cache_alloced, always alloc OK
 */
cache_line_t *
mmu_cache_alloc (ARMul_State * state, cache_s * cache_t, ARMword va,
		 ARMword pa)
{
	cache_line_t *cache;
	cache_set_t *set;
	int i;

	va = va_cache_align (va, cache_t);
	pa = va_cache_align (pa, cache_t);

	set = &cache_t->sets[va_cache_set (va, cache_t)];

	/*robin-round */
	cache = &set->lines[set->cycle++];
	if (set->cycle == cache_t->way)
		set->cycle = 0;

	if (cache_t->w_mode == CACHE_WRITE_BACK) {
		ARMword t;

		/*if cache valid, try to write back */
		if (cache->tag & TAG_VALID_FLAG) {
			mmu_cache_write_back (state, cache_t, cache);
		}
		/*read in cache_line */
		t = pa;
		for (i = 0; i < (cache_t->width >> WORD_SHT);
		     i++, t += WORD_SIZE) {
			//cache->data[i] = mem_read_word (state, t);
			bus_read(32, t, &cache->data[i]);
		}
	}
	/*store tag and pa */
	cache->tag = va | TAG_VALID_FLAG;
	cache->pa = pa;

	return cache;
};

/* mmu_cache_write_back write cache data to memory
 * @state
 * @cache_t :cache_t of the cache line
 * @cache : cache line
 */
void
mmu_cache_write_back (ARMul_State * state, cache_s * cache_t,
		      cache_line_t * cache)
{
	ARMword pa = cache->pa;
	int nw = cache_t->width >> WORD_SHT;
	ARMword *data = cache->data;
	int i;
	int t0, t1, t2;

	if ((cache->tag & 1) == 0)
		return;

	switch (cache->
		tag & ~1 & (TAG_FIRST_HALF_DIRTY | TAG_LAST_HALF_DIRTY)) {
	case 0:
		return;
	case TAG_FIRST_HALF_DIRTY:
		nw /= 2;
		break;
	case TAG_LAST_HALF_DIRTY:
		nw /= 2;
		pa += nw << WORD_SHT;
		data += nw;
		break;
	case TAG_FIRST_HALF_DIRTY | TAG_LAST_HALF_DIRTY:
		break;
	}
	for (i = 0; i < nw; i++, data++, pa += WORD_SIZE)
		//mem_write_word (state, pa, *data);
		bus_write(32, pa, *data);

	cache->tag &= ~(TAG_FIRST_HALF_DIRTY | TAG_LAST_HALF_DIRTY);
};


/* mmu_cache_clean: clean a cache of va in cache_t
 *
 * @state	:ARMul_State
 * @cache_t	:cache_t to clean
 * @va		:virtaul address
 */
void
mmu_cache_clean (ARMul_State * state, cache_s * cache_t, ARMword va)
{
	cache_line_t *cache;

	cache = mmu_cache_search (state, cache_t, va);
	if (cache)
		mmu_cache_write_back (state, cache_t, cache);
}

/* mmu_cache_clean_by_index: clean a cache by set/index format value
 *
 * @state	:ARMul_State
 * @cache_t	:cache_t to clean
 * @va		:set/index format value
 */
void
mmu_cache_clean_by_index (ARMul_State * state, cache_s * cache_t,
			  ARMword index)
{
	cache_line_t *cache;

	cache = mmu_cache_search_by_index (state, cache_t, index);
	if (cache)
		mmu_cache_write_back (state, cache_t, cache);
}

/* mmu_cache_invalidate : invalidate a cache of va
 *
 * @state	:ARMul_State
 * @cache_t	:cache_t to invalid
 * @va		:virt_addr to invalid
 */
void
mmu_cache_invalidate (ARMul_State * state, cache_s * cache_t, ARMword va)
{
	cache_line_t *cache;

	cache = mmu_cache_search (state, cache_t, va);
	if (cache) {
		mmu_cache_write_back (state, cache_t, cache);
		cache->tag = 0;
	}
}

/* mmu_cache_invalidate_by_index : invalidate a cache by index format
 *
 * @state	:ARMul_State
 * @cache_t	:cache_t to invalid
 * @index	:set/index data
 */
void
mmu_cache_invalidate_by_index (ARMul_State * state, cache_s * cache_t,
			       ARMword index)
{
	cache_line_t *cache;

	cache = mmu_cache_search_by_index (state, cache_t, index);
	if (cache) {
		mmu_cache_write_back (state, cache_t, cache);
		cache->tag = 0;
	}
}

/* mmu_cache_invalidate_all
 *
 * @state:
 * @cache_t
 * */
void
mmu_cache_invalidate_all (ARMul_State * state, cache_s * cache_t)
{
	int i, j;
	cache_set_t *set;
	cache_line_t *cache;

	set = cache_t->sets;
	for (i = 0; i < cache_t->set; i++, set++) {
		cache = set->lines;
		for (j = 0; j < cache_t->way; j++, cache++) {
			mmu_cache_write_back (state, cache_t, cache);
			cache->tag = 0;
		}
	}
};

void
mmu_cache_soft_flush (ARMul_State * state, cache_s * cache_t, ARMword pa)
{
	ARMword set, way;
	cache_line_t *cache;
	pa = (pa / cache_t->width);
	way = pa & (cache_t->way - 1);
	set = (pa / cache_t->way) & (cache_t->set - 1);
	cache = &cache_t->sets[set].lines[way];

	mmu_cache_write_back (state, cache_t, cache);
	cache->tag = 0;
}

cache_line_t*  mmu_cache_dirty_cache(ARMul_State *state,cache_s *cache){
	int i;
	int j;
	cache_line_t *cache_line = NULL;
	cache_set_t *cache_set = cache->sets;
	int sets = cache->set;
	for (i = 0; i < sets; i++){
		for(j = 0,cache_line = &cache_set[i].lines[0]; j < cache->way; j++,cache_line++){
			if((cache_line->tag & TAG_FIRST_HALF_DIRTY) || (cache_line->tag & TAG_LAST_HALF_DIRTY))
				return cache_line;
		}
	}
	return NULL;
}