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-rw-r--r--src/video_core/regs_pipeline.h43
1 files changed, 40 insertions, 3 deletions
diff --git a/src/video_core/regs_pipeline.h b/src/video_core/regs_pipeline.h
index 31c747d77..e78c3e331 100644
--- a/src/video_core/regs_pipeline.h
+++ b/src/video_core/regs_pipeline.h
@@ -147,7 +147,15 @@ struct PipelineRegs {
// Number of vertices to render
u32 num_vertices;
- INSERT_PADDING_WORDS(0x1);
+ enum class UseGS : u32 {
+ No = 0,
+ Yes = 2,
+ };
+
+ union {
+ BitField<0, 2, UseGS> use_gs;
+ BitField<31, 1, u32> variable_primitive;
+ };
// The index of the first vertex to render
u32 vertex_offset;
@@ -202,7 +210,14 @@ struct PipelineRegs {
/// Number of input attributes to the vertex shader minus 1
BitField<0, 4, u32> max_input_attrib_index;
- INSERT_PADDING_WORDS(2);
+ INSERT_PADDING_WORDS(1);
+
+ // The shader unit 3, which can be used for both vertex and geometry shader, gets its
+ // configuration depending on this register. If this is not set, unit 3 will share some
+ // configuration with other units. It is known that program code and swizzle pattern uploaded
+ // via regs.vs will be also uploaded to unit 3 if this is not set. Although very likely, it is
+ // still unclear whether uniforms and other configuration can be also shared.
+ BitField<0, 1, u32> gs_unit_exclusive_configuration;
enum class GPUMode : u32 {
Drawing = 0,
@@ -211,7 +226,29 @@ struct PipelineRegs {
GPUMode gpu_mode;
- INSERT_PADDING_WORDS(0x18);
+ INSERT_PADDING_WORDS(0x4);
+ BitField<0, 4, u32> vs_outmap_total_minus_1_a;
+ INSERT_PADDING_WORDS(0x6);
+ BitField<0, 4, u32> vs_outmap_total_minus_1_b;
+
+ enum class GSMode : u32 {
+ Point = 0,
+ VariablePrimitive = 1,
+ FixedPrimitive = 2,
+ };
+
+ union {
+ BitField<0, 8, GSMode> mode;
+ BitField<8, 4, u32> fixed_vertex_num_minus_1;
+ BitField<12, 4, u32> stride_minus_1;
+ BitField<16, 4, u32> start_index;
+ } gs_config;
+
+ INSERT_PADDING_WORDS(0x1);
+
+ u32 variable_vertex_main_num_minus_1;
+
+ INSERT_PADDING_WORDS(0x9);
enum class TriangleTopology : u32 {
List = 0,