diff options
Diffstat (limited to 'src/video_core/engines')
-rw-r--r-- | src/video_core/engines/maxwell_3d.cpp | 15 | ||||
-rw-r--r-- | src/video_core/engines/maxwell_3d.h | 17 |
2 files changed, 30 insertions, 2 deletions
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp index a0dd7400d..50d8a94b1 100644 --- a/src/video_core/engines/maxwell_3d.cpp +++ b/src/video_core/engines/maxwell_3d.cpp @@ -182,8 +182,14 @@ u32 Maxwell3D::GetMaxCurrentVertices() { size_t Maxwell3D::EstimateIndexBufferSize() { GPUVAddr start_address = regs.index_buffer.StartAddress(); GPUVAddr end_address = regs.index_buffer.EndAddress(); - return std::min<size_t>(memory_manager.GetMemoryLayoutSize(start_address), - static_cast<size_t>(end_address - start_address)); + constexpr std::array<size_t, 4> max_sizes = { + std::numeric_limits<u8>::max(), std::numeric_limits<u16>::max(), + std::numeric_limits<u32>::max(), std::numeric_limits<u32>::max()}; + const size_t byte_size = regs.index_buffer.FormatSizeInBytes(); + return std::min<size_t>( + memory_manager.GetMemoryLayoutSize(start_address, byte_size * max_sizes[byte_size]) / + byte_size, + static_cast<size_t>(end_address - start_address)); } u32 Maxwell3D::ProcessShadowRam(u32 method, u32 argument) { @@ -572,4 +578,9 @@ u32 Maxwell3D::GetRegisterValue(u32 method) const { return regs.reg_array[method]; } +void Maxwell3D::setHLEReplacementName(u32 bank, u32 offset, HLEReplaceName name) { + const u64 key = (static_cast<u64>(bank) << 32) | offset; + replace_table.emplace(key, name); +} + } // namespace Tegra::Engines diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h index cfe1e4883..397e88f67 100644 --- a/src/video_core/engines/maxwell_3d.h +++ b/src/video_core/engines/maxwell_3d.h @@ -3020,6 +3020,23 @@ public: /// Store temporary hw register values, used by some calls to restore state after a operation Regs shadow_state; + // None Engine + enum class EngineHint : u32 { + None = 0x0, + OnHLEMacro = 0x1, + }; + + EngineHint engine_state{EngineHint::None}; + + enum class HLEReplaceName : u32 { + BaseVertex = 0x0, + BaseInstance = 0x1, + }; + + void setHLEReplacementName(u32 bank, u32 offset, HLEReplaceName name); + + std::unordered_map<u64, HLEReplaceName> replace_table; + static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32), "Maxwell3D Regs has wrong size"); static_assert(std::is_trivially_copyable_v<Regs>, "Maxwell3D Regs must be trivially copyable"); |