summaryrefslogtreecommitdiffstats
path: root/src
diff options
context:
space:
mode:
authorFernando Sahmkow <fsahmkow27@gmail.com>2019-04-25 18:57:10 +0200
committerFernandoS27 <fsahmkow27@gmail.com>2019-05-01 21:31:39 +0200
commite64c41efe88e8f88014fef912b06b71b3df17e85 (patch)
tree626793bd10db844237b8136154ea6b81fe72e4b1 /src
parentFixes and Corrections to DMA Engine (diff)
downloadyuzu-e64c41efe88e8f88014fef912b06b71b3df17e85.tar
yuzu-e64c41efe88e8f88014fef912b06b71b3df17e85.tar.gz
yuzu-e64c41efe88e8f88014fef912b06b71b3df17e85.tar.bz2
yuzu-e64c41efe88e8f88014fef912b06b71b3df17e85.tar.lz
yuzu-e64c41efe88e8f88014fef912b06b71b3df17e85.tar.xz
yuzu-e64c41efe88e8f88014fef912b06b71b3df17e85.tar.zst
yuzu-e64c41efe88e8f88014fef912b06b71b3df17e85.zip
Diffstat (limited to 'src')
-rw-r--r--src/video_core/engines/engine_upload.cpp39
-rw-r--r--src/video_core/engines/engine_upload.h9
-rw-r--r--src/video_core/engines/kepler_compute.h4
-rw-r--r--src/video_core/engines/kepler_memory.h2
-rw-r--r--src/video_core/engines/maxwell_3d.h2
-rw-r--r--src/video_core/engines/maxwell_dma.h14
6 files changed, 35 insertions, 35 deletions
diff --git a/src/video_core/engines/engine_upload.cpp b/src/video_core/engines/engine_upload.cpp
index 867457f25..f8aa4ff55 100644
--- a/src/video_core/engines/engine_upload.cpp
+++ b/src/video_core/engines/engine_upload.cpp
@@ -9,7 +9,7 @@
namespace Tegra::Engines::Upload {
-State::State(MemoryManager& memory_manager, Data& regs)
+State::State(MemoryManager& memory_manager, Registers& regs)
: memory_manager(memory_manager), regs(regs) {}
void State::ProcessExec(const bool is_linear) {
@@ -23,24 +23,25 @@ void State::ProcessData(const u32 data, const bool is_last_call) {
const u32 sub_copy_size = std::min(4U, copy_size - write_offset);
std::memcpy(&inner_buffer[write_offset], &data, sub_copy_size);
write_offset += sub_copy_size;
- if (is_last_call) {
- const GPUVAddr address{regs.dest.Address()};
- if (is_linear) {
- memory_manager.WriteBlock(address, inner_buffer.data(), copy_size);
- } else {
- UNIMPLEMENTED_IF(regs.dest.z != 0);
- UNIMPLEMENTED_IF(regs.dest.depth != 1);
- UNIMPLEMENTED_IF(regs.dest.BlockWidth() != 1);
- UNIMPLEMENTED_IF(regs.dest.BlockDepth() != 1);
- const std::size_t dst_size = Tegra::Texture::CalculateSize(
- true, 1, regs.dest.width, regs.dest.height, 1, regs.dest.BlockHeight(), 1);
- std::vector<u8> tmp_buffer(dst_size);
- memory_manager.ReadBlock(address, tmp_buffer.data(), dst_size);
- Tegra::Texture::SwizzleKepler(regs.dest.width, regs.dest.height, regs.dest.x,
- regs.dest.y, regs.dest.BlockHeight(), copy_size,
- inner_buffer.data(), tmp_buffer.data());
- memory_manager.WriteBlock(address, tmp_buffer.data(), dst_size);
- }
+ if (!is_last_call) {
+ return;
+ }
+ const GPUVAddr address{regs.dest.Address()};
+ if (is_linear) {
+ memory_manager.WriteBlock(address, inner_buffer.data(), copy_size);
+ } else {
+ UNIMPLEMENTED_IF(regs.dest.z != 0);
+ UNIMPLEMENTED_IF(regs.dest.depth != 1);
+ UNIMPLEMENTED_IF(regs.dest.BlockWidth() != 1);
+ UNIMPLEMENTED_IF(regs.dest.BlockDepth() != 1);
+ const std::size_t dst_size = Tegra::Texture::CalculateSize(
+ true, 1, regs.dest.width, regs.dest.height, 1, regs.dest.BlockHeight(), 1);
+ tmp_buffer.resize(dst_size);
+ memory_manager.ReadBlock(address, tmp_buffer.data(), dst_size);
+ Tegra::Texture::SwizzleKepler(regs.dest.width, regs.dest.height, regs.dest.x, regs.dest.y,
+ regs.dest.BlockHeight(), copy_size, inner_buffer.data(),
+ tmp_buffer.data());
+ memory_manager.WriteBlock(address, tmp_buffer.data(), dst_size);
}
}
diff --git a/src/video_core/engines/engine_upload.h b/src/video_core/engines/engine_upload.h
index 431f56030..9c6e0d21c 100644
--- a/src/video_core/engines/engine_upload.h
+++ b/src/video_core/engines/engine_upload.h
@@ -16,7 +16,7 @@ class MemoryManager;
namespace Tegra::Engines::Upload {
-struct Data {
+struct Registers {
u32 line_length_in;
u32 line_count;
@@ -56,7 +56,7 @@ struct Data {
class State {
public:
- State(MemoryManager& memory_manager, Data& regs);
+ State(MemoryManager& memory_manager, Registers& regs);
~State() = default;
void ProcessExec(const bool is_linear);
@@ -66,8 +66,9 @@ private:
u32 write_offset = 0;
u32 copy_size = 0;
std::vector<u8> inner_buffer;
- bool is_linear;
- Data& regs;
+ std::vector<u8> tmp_buffer;
+ bool is_linear = false;
+ Registers& regs;
MemoryManager& memory_manager;
};
diff --git a/src/video_core/engines/kepler_compute.h b/src/video_core/engines/kepler_compute.h
index 50f318848..5250b8d9b 100644
--- a/src/video_core/engines/kepler_compute.h
+++ b/src/video_core/engines/kepler_compute.h
@@ -51,7 +51,7 @@ public:
struct {
INSERT_PADDING_WORDS(0x60);
- Upload::Data upload;
+ Upload::Registers upload;
struct {
union {
@@ -131,7 +131,6 @@ public:
BitField<30, 1, u32> linked_tsc;
BitField<0, 31, u32> grid_dim_x;
-
union {
BitField<0, 16, u32> grid_dim_y;
BitField<16, 16, u32> grid_dim_z;
@@ -142,7 +141,6 @@ public:
BitField<0, 16, u32> shared_alloc;
BitField<0, 31, u32> block_dim_x;
-
union {
BitField<0, 16, u32> block_dim_y;
BitField<16, 16, u32> block_dim_z;
diff --git a/src/video_core/engines/kepler_memory.h b/src/video_core/engines/kepler_memory.h
index 473bff20a..f3bc675a9 100644
--- a/src/video_core/engines/kepler_memory.h
+++ b/src/video_core/engines/kepler_memory.h
@@ -47,7 +47,7 @@ public:
struct {
INSERT_PADDING_WORDS(0x60);
- Upload::Data upload;
+ Upload::Registers upload;
struct {
union {
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index eae427412..889723535 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -588,7 +588,7 @@ public:
INSERT_PADDING_WORDS(0x17);
- Upload::Data upload;
+ Upload::Registers upload;
struct {
union {
BitField<0, 1, u32> linear;
diff --git a/src/video_core/engines/maxwell_dma.h b/src/video_core/engines/maxwell_dma.h
index 8eab1332e..e5942f671 100644
--- a/src/video_core/engines/maxwell_dma.h
+++ b/src/video_core/engines/maxwell_dma.h
@@ -70,13 +70,13 @@ public:
static_assert(sizeof(Parameters) == 24, "Parameters has wrong size");
enum class ComponentMode : u32 {
- SRC0 = 0,
- SRC1 = 1,
- SRC2 = 2,
- SRC3 = 3,
- CONST0 = 4,
- CONST1 = 5,
- ZERO = 6,
+ Src0 = 0,
+ Src1 = 1,
+ Src2 = 2,
+ Src3 = 3,
+ Const0 = 4,
+ Const1 = 5,
+ Zero = 6,
};
enum class CopyMode : u32 {