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author | Subv <subv2112@gmail.com> | 2018-03-19 06:36:25 +0100 |
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committer | Subv <subv2112@gmail.com> | 2018-03-19 06:36:25 +0100 |
commit | dcae0c9a4fb950784db36b372c21aef718551eb5 (patch) | |
tree | 07a410fab9206504f24b779b6631efc41e485142 /src | |
parent | GPU: Added the TIC registers to the Maxwell3D register structure. (diff) | |
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Diffstat (limited to 'src')
-rw-r--r-- | src/video_core/engines/maxwell_3d.h | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h index 272ebee31..096679162 100644 --- a/src/video_core/engines/maxwell_3d.h +++ b/src/video_core/engines/maxwell_3d.h @@ -62,7 +62,20 @@ public: union { struct { - INSERT_PADDING_WORDS(0x55D); + INSERT_PADDING_WORDS(0x557); + + struct { + u32 tsc_address_high; + u32 tsc_address_low; + u32 tsc_limit; + + GPUVAddr TSCAddress() const { + return static_cast<GPUVAddr>( + (static_cast<GPUVAddr>(tsc_address_high) << 32) | tsc_address_low); + } + } tsc; + + INSERT_PADDING_WORDS(0x3); struct { u32 tic_address_high; @@ -278,6 +291,7 @@ private: static_assert(offsetof(Maxwell3D::Regs, field_name) == position * 4, \ "Field " #field_name " has invalid position") +ASSERT_REG_POSITION(tsc, 0x557); ASSERT_REG_POSITION(tic, 0x55D); ASSERT_REG_POSITION(code_address, 0x582); ASSERT_REG_POSITION(draw, 0x585); |