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authorReinUsesLisp <reinuseslisp@airmail.cc>2018-12-21 03:55:19 +0100
committerReinUsesLisp <reinuseslisp@airmail.cc>2019-01-15 21:54:50 +0100
commit4ccaa1402d376af14d8527c0a0bcc77be007bd3c (patch)
treee7e91a50052583966f7963d4a440dd56b2ddb2d6 /src/video_core
parentshader_decode: Implement FMUL_C, FMUL_R and FMUL_IMM (diff)
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Diffstat (limited to 'src/video_core')
-rw-r--r--src/video_core/shader/decode/arithmetic.cpp15
1 files changed, 15 insertions, 0 deletions
diff --git a/src/video_core/shader/decode/arithmetic.cpp b/src/video_core/shader/decode/arithmetic.cpp
index 78bca79e3..d196d94b5 100644
--- a/src/video_core/shader/decode/arithmetic.cpp
+++ b/src/video_core/shader/decode/arithmetic.cpp
@@ -78,6 +78,21 @@ u32 ShaderIR::DecodeArithmetic(BasicBlock& bb, u32 pc) {
SetRegister(bb, instr.gpr0, value);
break;
}
+ case OpCode::Id::FADD_C:
+ case OpCode::Id::FADD_R:
+ case OpCode::Id::FADD_IMM: {
+ UNIMPLEMENTED_IF_MSG(instr.generates_cc,
+ "Condition codes generation in FADD is not implemented");
+
+ op_a = GetOperandAbsNegFloat(op_a, instr.alu.abs_a, instr.alu.negate_a);
+ op_b = GetOperandAbsNegFloat(op_b, instr.alu.abs_b, instr.alu.negate_b);
+
+ Node value = Operation(OperationCode::FAdd, PRECISE, op_a, op_b);
+ value = GetSaturatedFloat(value, instr.alu.saturate_d);
+
+ SetRegister(bb, instr.gpr0, value);
+ break;
+ }
default:
UNIMPLEMENTED_MSG("Unhandled arithmetic instruction: {}", opcode->get().GetName());
}