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authorReinUsesLisp <reinuseslisp@airmail.cc>2018-12-21 03:53:50 +0100
committerReinUsesLisp <reinuseslisp@airmail.cc>2019-01-15 21:54:50 +0100
commit4c70d5b8eb68a61f5504a05dd597ecb2b04441b5 (patch)
treed3c102f2bf3a74819aff17c13956175db38ebaaf /src/video_core
parentvideo_core: Replace gl_shader_decompiler (diff)
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Diffstat (limited to 'src/video_core')
-rw-r--r--src/video_core/shader/decode/arithmetic.cpp24
1 files changed, 23 insertions, 1 deletions
diff --git a/src/video_core/shader/decode/arithmetic.cpp b/src/video_core/shader/decode/arithmetic.cpp
index 9242a7389..c297f729e 100644
--- a/src/video_core/shader/decode/arithmetic.cpp
+++ b/src/video_core/shader/decode/arithmetic.cpp
@@ -11,12 +11,34 @@ namespace VideoCommon::Shader {
using Tegra::Shader::Instruction;
using Tegra::Shader::OpCode;
+using Tegra::Shader::SubOp;
u32 ShaderIR::DecodeArithmetic(BasicBlock& bb, u32 pc) {
const Instruction instr = {program_code[pc]};
const auto opcode = OpCode::Decode(instr);
- UNIMPLEMENTED();
+ Node op_a = GetRegister(instr.gpr8);
+
+ Node op_b = [&]() -> Node {
+ if (instr.is_b_imm) {
+ return GetImmediate19(instr);
+ } else if (instr.is_b_gpr) {
+ return GetRegister(instr.gpr20);
+ } else {
+ return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset);
+ }
+ }();
+
+ switch (opcode->get().GetId()) {
+ case OpCode::Id::MOV_C:
+ case OpCode::Id::MOV_R: {
+ // MOV does not have neither 'abs' nor 'neg' bits.
+ SetRegister(bb, instr.gpr0, op_b);
+ break;
+ }
+ default:
+ UNIMPLEMENTED_MSG("Unhandled arithmetic instruction: {}", opcode->get().GetName());
+ }
return pc;
}