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author | ReinUsesLisp <reinuseslisp@airmail.cc> | 2018-12-21 02:41:31 +0100 |
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committer | ReinUsesLisp <reinuseslisp@airmail.cc> | 2019-01-15 21:54:49 +0100 |
commit | 5e639bfcf6d764714cc9814fc47142ca85f889cf (patch) | |
tree | 29f4a84ea1beb8636352f10b0e6513977b3ed50d /src/video_core/shader | |
parent | shader_ir: Add immediate node constructors (diff) | |
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Diffstat (limited to 'src/video_core/shader')
-rw-r--r-- | src/video_core/shader/shader_ir.cpp | 7 | ||||
-rw-r--r-- | src/video_core/shader/shader_ir.h | 2 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/video_core/shader/shader_ir.cpp b/src/video_core/shader/shader_ir.cpp index c59ecf457..ff4e462f2 100644 --- a/src/video_core/shader/shader_ir.cpp +++ b/src/video_core/shader/shader_ir.cpp @@ -39,6 +39,13 @@ Node ShaderIR::Immediate(u32 value) { return StoreNode(ImmediateNode(value)); } +Node ShaderIR::GetRegister(Register reg) { + if (reg != Register::ZeroIndex) { + used_registers.insert(static_cast<u32>(reg)); + } + return StoreNode(GprNode(reg)); +} + Node ShaderIR::GetImmediate19(Instruction instr) { return Immediate(instr.alu.GetImm20_19()); } diff --git a/src/video_core/shader/shader_ir.h b/src/video_core/shader/shader_ir.h index db06d51ca..30b75c3ed 100644 --- a/src/video_core/shader/shader_ir.h +++ b/src/video_core/shader/shader_ir.h @@ -610,6 +610,8 @@ private: return Immediate(*reinterpret_cast<const u32*>(&value)); } + /// Generates a node for a passed register. + Node GetRegister(Tegra::Shader::Register reg); /// Generates a node representing a 19-bit immediate value Node GetImmediate19(Tegra::Shader::Instruction instr); /// Generates a node representing a 32-bit immediate value |