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author | ReinUsesLisp <reinuseslisp@airmail.cc> | 2018-12-21 06:13:00 +0100 |
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committer | ReinUsesLisp <reinuseslisp@airmail.cc> | 2019-01-15 21:54:51 +0100 |
commit | 078ba28e13b4ecd7fe51e361a577a178faa74b3f (patch) | |
tree | bb76dd1122859d988237fe15156d6d1975aa92a4 /src/video_core/shader | |
parent | shader_decode: Implement LD_C (diff) | |
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Diffstat (limited to 'src/video_core/shader')
-rw-r--r-- | src/video_core/shader/decode/integer_set.cpp | 28 |
1 files changed, 27 insertions, 1 deletions
diff --git a/src/video_core/shader/decode/integer_set.cpp b/src/video_core/shader/decode/integer_set.cpp index 316a7d8ad..eba1c5123 100644 --- a/src/video_core/shader/decode/integer_set.cpp +++ b/src/video_core/shader/decode/integer_set.cpp @@ -16,7 +16,33 @@ u32 ShaderIR::DecodeIntegerSet(BasicBlock& bb, u32 pc) { const Instruction instr = {program_code[pc]}; const auto opcode = OpCode::Decode(instr); - UNIMPLEMENTED(); + const Node op_a = GetRegister(instr.gpr8); + const Node op_b = [&]() { + if (instr.is_b_imm) { + return Immediate(instr.alu.GetSignedImm20_20()); + } else if (instr.is_b_gpr) { + return GetRegister(instr.gpr20); + } else { + return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset); + } + }(); + + // The iset instruction sets a register to 1.0 or -1 (depending on the bf bit) if the condition + // is true, and to 0 otherwise. + const Node second_pred = GetPredicate(instr.iset.pred39, instr.iset.neg_pred != 0); + const Node first_pred = + GetPredicateComparisonInteger(instr.iset.cond, instr.iset.is_signed, op_a, op_b); + + const OperationCode combiner = GetPredicateCombiner(instr.iset.op); + + const Node predicate = Operation(combiner, first_pred, second_pred); + + const Node true_value = instr.iset.bf ? Immediate(1.0f) : Immediate(-1); + const Node false_value = instr.iset.bf ? Immediate(0.0f) : Immediate(0); + const Node value = + Operation(OperationCode::Select, PRECISE, predicate, true_value, false_value); + + SetRegister(bb, instr.gpr0, value); return pc; } |