diff options
author | Fernando Sahmkow <fsahmkow27@gmail.com> | 2019-11-18 12:34:34 +0100 |
---|---|---|
committer | Fernando Sahmkow <fsahmkow27@gmail.com> | 2019-11-18 12:34:34 +0100 |
commit | c8473f399e745993d2b9980f4ef62fa6a208ec3d (patch) | |
tree | af8d64c9a361cb600ec2521f05b5faef0bb76da0 /src/video_core/shader/decode/arithmetic_integer.cpp | |
parent | Shader_IR: Implement TXD instruction. (diff) | |
download | yuzu-c8473f399e745993d2b9980f4ef62fa6a208ec3d.tar yuzu-c8473f399e745993d2b9980f4ef62fa6a208ec3d.tar.gz yuzu-c8473f399e745993d2b9980f4ef62fa6a208ec3d.tar.bz2 yuzu-c8473f399e745993d2b9980f4ef62fa6a208ec3d.tar.lz yuzu-c8473f399e745993d2b9980f4ef62fa6a208ec3d.tar.xz yuzu-c8473f399e745993d2b9980f4ef62fa6a208ec3d.tar.zst yuzu-c8473f399e745993d2b9980f4ef62fa6a208ec3d.zip |
Diffstat (limited to 'src/video_core/shader/decode/arithmetic_integer.cpp')
-rw-r--r-- | src/video_core/shader/decode/arithmetic_integer.cpp | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/src/video_core/shader/decode/arithmetic_integer.cpp b/src/video_core/shader/decode/arithmetic_integer.cpp index 9208b7bef..371fae127 100644 --- a/src/video_core/shader/decode/arithmetic_integer.cpp +++ b/src/video_core/shader/decode/arithmetic_integer.cpp @@ -135,17 +135,18 @@ u32 ShaderIR::DecodeArithmeticInteger(NodeBlock& bb, u32 pc) { case OpCode::Id::FLO_IMM: { Node value; if (instr.flo.invert) { - op_b = Operation(OperationCode::IBitwiseNot, NO_PRECISE, op_b); + op_b = Operation(OperationCode::IBitwiseNot, NO_PRECISE, std::move(op_b)); } if (instr.flo.is_signed) { - value = Operation(OperationCode::IBitMSB, NO_PRECISE, op_b); + value = Operation(OperationCode::IBitMSB, NO_PRECISE, std::move(op_b)); } else { - value = Operation(OperationCode::UBitMSB, NO_PRECISE, op_b); + value = Operation(OperationCode::UBitMSB, NO_PRECISE, std::move(op_b)); } if (instr.flo.sh) { - value = Operation(OperationCode::UBitwiseXor, NO_PRECISE, value, Immediate(31)); + value = + Operation(OperationCode::UBitwiseXor, NO_PRECISE, std::move(value), Immediate(31)); } - SetRegister(bb, instr.gpr0, value); + SetRegister(bb, instr.gpr0, std::move(value)); break; } case OpCode::Id::SEL_C: |