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| author | bunnei <bunneidev@gmail.com> | 2018-06-09 06:34:03 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-06-09 06:34:03 +0200 |
| commit | 174c22e5f6a1fd93842a8e8fda6e63e676d34866 (patch) | |
| tree | ac8613849062fe64ed2e8ddd02dbedf5e381ecaa /src/video_core/engines | |
| parent | Merge pull request #505 from janisozaur/ccache-travis (diff) | |
| parent | gl_shader_decompiler: Implement IADD instruction. (diff) | |
| download | yuzu-174c22e5f6a1fd93842a8e8fda6e63e676d34866.tar yuzu-174c22e5f6a1fd93842a8e8fda6e63e676d34866.tar.gz yuzu-174c22e5f6a1fd93842a8e8fda6e63e676d34866.tar.bz2 yuzu-174c22e5f6a1fd93842a8e8fda6e63e676d34866.tar.lz yuzu-174c22e5f6a1fd93842a8e8fda6e63e676d34866.tar.xz yuzu-174c22e5f6a1fd93842a8e8fda6e63e676d34866.tar.zst yuzu-174c22e5f6a1fd93842a8e8fda6e63e676d34866.zip | |
Diffstat (limited to 'src/video_core/engines')
| -rw-r--r-- | src/video_core/engines/shader_bytecode.h | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 32800392b..dc3dd8a80 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h @@ -213,6 +213,7 @@ union Instruction { BitField<28, 8, Register> gpr28; BitField<39, 8, Register> gpr39; BitField<48, 16, u64> opcode; + BitField<50, 1, u64> saturate_a; union { BitField<20, 19, u64> imm20_19; @@ -263,7 +264,7 @@ union Instruction { BitField<39, 5, u64> shift_amount; BitField<48, 1, u64> negate_b; BitField<49, 1, u64> negate_a; - } iscadd; + } alu_integer; union { BitField<20, 8, u64> shift_position; @@ -331,7 +332,6 @@ union Instruction { BitField<41, 2, u64> selector; BitField<45, 1, u64> negate_a; BitField<49, 1, u64> abs_a; - BitField<50, 1, u64> saturate_a; union { BitField<39, 2, F2iRoundingOp> rounding; @@ -434,6 +434,9 @@ public: FMUL_R, FMUL_IMM, FMUL32_IMM, + IADD_C, + IADD_R, + IADD_IMM, ISCADD_C, // Scale and Add ISCADD_R, ISCADD_IMM, @@ -489,10 +492,10 @@ public: enum class Type { Trivial, Arithmetic, + ArithmeticInteger, Bfe, Logic, Shift, - ScaledAdd, Ffma, Flow, Memory, @@ -617,9 +620,12 @@ private: INST("0101110001101---", Id::FMUL_R, Type::Arithmetic, "FMUL_R"), INST("0011100-01101---", Id::FMUL_IMM, Type::Arithmetic, "FMUL_IMM"), INST("00011110--------", Id::FMUL32_IMM, Type::Arithmetic, "FMUL32_IMM"), - INST("0100110000011---", Id::ISCADD_C, Type::ScaledAdd, "ISCADD_C"), - INST("0101110000011---", Id::ISCADD_R, Type::ScaledAdd, "ISCADD_R"), - INST("0011100-00011---", Id::ISCADD_IMM, Type::ScaledAdd, "ISCADD_IMM"), + INST("0100110000010---", Id::IADD_C, Type::ArithmeticInteger, "IADD_C"), + INST("0101110000010---", Id::IADD_R, Type::ArithmeticInteger, "IADD_R"), + INST("0011100-00010---", Id::IADD_IMM, Type::ArithmeticInteger, "IADD_IMM"), + INST("0100110000011---", Id::ISCADD_C, Type::ArithmeticInteger, "ISCADD_C"), + INST("0101110000011---", Id::ISCADD_R, Type::ArithmeticInteger, "ISCADD_R"), + INST("0011100-00011---", Id::ISCADD_IMM, Type::ArithmeticInteger, "ISCADD_IMM"), INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"), INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"), INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"), |