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author | Subv <subv2112@gmail.com> | 2018-06-09 23:19:13 +0200 |
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committer | Subv <subv2112@gmail.com> | 2018-06-09 23:19:13 +0200 |
commit | b366b885a13623e13afba36e52765d949bb05766 (patch) | |
tree | ad1a89a8b7686e2947e7eca53716e4e45e27085d /src/video_core/engines/shader_bytecode.h | |
parent | GPU: Added decodings for the ISET family of instructions. (diff) | |
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Diffstat (limited to 'src/video_core/engines/shader_bytecode.h')
-rw-r--r-- | src/video_core/engines/shader_bytecode.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 9f17225f8..ec8dbd370 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h @@ -330,6 +330,15 @@ union Instruction { } fset; union { + BitField<39, 3, u64> pred39; + BitField<42, 1, u64> neg_pred; + BitField<44, 1, u64> bf; + BitField<45, 2, PredOperation> op; + BitField<48, 1, u64> is_signed; + BitField<49, 3, PredCondition> cond; + } iset; + + union { BitField<10, 2, Register::Size> size; BitField<12, 1, u64> is_output_signed; BitField<13, 1, u64> is_input_signed; |