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| author | bunnei <bunneidev@gmail.com> | 2018-10-11 03:24:07 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-10-11 03:24:07 +0200 |
| commit | 6d82c4adf92f743eadf0749bf01646baaabfa735 (patch) | |
| tree | 5a5a9aa040e600202bee1c99c74a6bfc57e1b52a /src/video_core/engines/maxwell_3d.h | |
| parent | Merge pull request #1460 from FernandoS27/scissor_test (diff) | |
| parent | Add memory Layout to Render Targets and Depth Buffers (diff) | |
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Diffstat (limited to 'src/video_core/engines/maxwell_3d.h')
| -rw-r--r-- | src/video_core/engines/maxwell_3d.h | 24 |
1 files changed, 22 insertions, 2 deletions
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h index 20e1884da..c8d1b6478 100644 --- a/src/video_core/engines/maxwell_3d.h +++ b/src/video_core/engines/maxwell_3d.h @@ -347,6 +347,16 @@ public: DecrWrap = 8, }; + enum class MemoryLayout : u32 { + Linear = 0, + BlockLinear = 1, + }; + + enum class InvMemoryLayout : u32 { + BlockLinear = 0, + Linear = 1, + }; + struct Cull { enum class FrontFace : u32 { ClockWise = 0x0900, @@ -432,7 +442,12 @@ public: u32 width; u32 height; Tegra::RenderTargetFormat format; - u32 block_dimensions; + union { + BitField<0, 3, u32> block_width; + BitField<4, 3, u32> block_height; + BitField<8, 3, u32> block_depth; + BitField<12, 1, InvMemoryLayout> type; + } memory_layout; u32 array_mode; u32 layer_stride; u32 base_layer; @@ -562,7 +577,12 @@ public: u32 address_high; u32 address_low; Tegra::DepthFormat format; - u32 block_dimensions; + union { + BitField<0, 4, u32> block_width; + BitField<4, 4, u32> block_height; + BitField<8, 4, u32> block_depth; + BitField<20, 1, InvMemoryLayout> type; + } memory_layout; u32 layer_stride; GPUVAddr Address() const { |