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authorReinUsesLisp <reinuseslisp@airmail.cc>2021-05-19 02:30:24 +0200
committerameerj <52414509+ameerj@users.noreply.github.com>2021-07-23 03:51:32 +0200
commit98ed8ff103a975be93dbbb89d554fbea355aacde (patch)
treeaaeed1b3c418544d9be14353cadcc4ad4d083006 /src/shader_recompiler
parentglasm: Implement SelectU1 (diff)
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Diffstat (limited to 'src/shader_recompiler')
-rw-r--r--src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp b/src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp
index 1befeca91..ba69c7a1b 100644
--- a/src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp
+++ b/src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp
@@ -122,6 +122,14 @@ void EmitBitFieldUExtract(EmitContext& ctx, IR::Inst& inst, ScalarU32 base, Scal
"BFE.U {},RC,{};",
count, offset, ret, base);
}
+ if (const auto zero = inst.GetAssociatedPseudoOperation(IR::Opcode::GetZeroFromOp)) {
+ ctx.Add("SEQ.S {},{},0;", *zero, ret);
+ zero->Invalidate();
+ }
+ if (const auto sign = inst.GetAssociatedPseudoOperation(IR::Opcode::GetSignFromOp)) {
+ ctx.Add("SLT.S {},{},0;", *sign, ret);
+ sign->Invalidate();
+ }
}
void EmitBitReverse32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value) {