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authorReinUsesLisp <reinuseslisp@airmail.cc>2021-05-18 09:04:06 +0200
committerameerj <52414509+ameerj@users.noreply.github.com>2021-07-23 03:51:32 +0200
commit1ee7f8b943d1ab6ac6dec18bae6c2be3fd8d246c (patch)
tree0967ae40a8bfc7f557e5a8c399bb9f18200d178a /src/shader_recompiler/backend
parentshader: Read branch conditions from an instruction (diff)
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Diffstat (limited to 'src/shader_recompiler/backend')
-rw-r--r--src/shader_recompiler/backend/glasm/emit_glasm_bitwise_conversion.cpp4
-rw-r--r--src/shader_recompiler/backend/glasm/reg_alloc.cpp1
2 files changed, 2 insertions, 3 deletions
diff --git a/src/shader_recompiler/backend/glasm/emit_glasm_bitwise_conversion.cpp b/src/shader_recompiler/backend/glasm/emit_glasm_bitwise_conversion.cpp
index 505378bfd..808c72105 100644
--- a/src/shader_recompiler/backend/glasm/emit_glasm_bitwise_conversion.cpp
+++ b/src/shader_recompiler/backend/glasm/emit_glasm_bitwise_conversion.cpp
@@ -22,8 +22,8 @@ void EmitIdentity(EmitContext&, IR::Inst& inst, const IR::Value& value) {
Alias(inst, value);
}
-void EmitConditionRef(EmitContext&, IR::Inst& inst, const IR::Value& value) {
- Alias(inst, value);
+void EmitConditionRef(EmitContext& ctx, IR::Inst& inst, const IR::Value& value) {
+ ctx.Add("MOV.S {},{};", inst, ScalarS32{ctx.reg_alloc.Consume(value)});
}
void EmitBitCastU16F16(EmitContext&, IR::Inst& inst, const IR::Value& value) {
diff --git a/src/shader_recompiler/backend/glasm/reg_alloc.cpp b/src/shader_recompiler/backend/glasm/reg_alloc.cpp
index 1a88331b4..707b22247 100644
--- a/src/shader_recompiler/backend/glasm/reg_alloc.cpp
+++ b/src/shader_recompiler/backend/glasm/reg_alloc.cpp
@@ -139,7 +139,6 @@ void RegAlloc::Free(Id id) {
/*static*/ bool RegAlloc::IsAliased(const IR::Inst& inst) {
switch (inst.GetOpcode()) {
case IR::Opcode::Identity:
- case IR::Opcode::ConditionRef:
case IR::Opcode::BitCastU16F16:
case IR::Opcode::BitCastU32F32:
case IR::Opcode::BitCastU64F64: