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authorReinUsesLisp <reinuseslisp@airmail.cc>2021-02-16 08:10:22 +0100
committerameerj <52414509+ameerj@users.noreply.github.com>2021-07-23 03:51:22 +0200
commitb5d7279d878211654b4abb165d94af763a365f47 (patch)
tree9b3a7b6e9d7d2b8945fe87d27ff75f1712ef06aa /src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
parentshader: Improve object pool (diff)
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Diffstat (limited to 'src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp')
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
index e811a63ab..32af94a73 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
@@ -10,7 +10,7 @@ Id EmitSPIRV::EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
if (inst->HasAssociatedPseudoOperation()) {
throw NotImplementedException("Pseudo-operations on IAdd32");
}
- return ctx.OpIAdd(ctx.u32[1], a, b);
+ return ctx.OpIAdd(ctx.U32[1], a, b);
}
void EmitSPIRV::EmitIAdd64(EmitContext&) {
@@ -18,7 +18,7 @@ void EmitSPIRV::EmitIAdd64(EmitContext&) {
}
Id EmitSPIRV::EmitISub32(EmitContext& ctx, Id a, Id b) {
- return ctx.OpISub(ctx.u32[1], a, b);
+ return ctx.OpISub(ctx.U32[1], a, b);
}
void EmitSPIRV::EmitISub64(EmitContext&) {
@@ -26,7 +26,7 @@ void EmitSPIRV::EmitISub64(EmitContext&) {
}
Id EmitSPIRV::EmitIMul32(EmitContext& ctx, Id a, Id b) {
- return ctx.OpIMul(ctx.u32[1], a, b);
+ return ctx.OpIMul(ctx.U32[1], a, b);
}
void EmitSPIRV::EmitINeg32(EmitContext&) {
@@ -38,7 +38,7 @@ void EmitSPIRV::EmitIAbs32(EmitContext&) {
}
Id EmitSPIRV::EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) {
- return ctx.OpShiftLeftLogical(ctx.u32[1], base, shift);
+ return ctx.OpShiftLeftLogical(ctx.U32[1], base, shift);
}
void EmitSPIRV::EmitShiftRightLogical32(EmitContext&) {
@@ -70,11 +70,11 @@ void EmitSPIRV::EmitBitFieldSExtract(EmitContext&) {
}
Id EmitSPIRV::EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count) {
- return ctx.OpBitFieldUExtract(ctx.u32[1], base, offset, count);
+ return ctx.OpBitFieldUExtract(ctx.U32[1], base, offset, count);
}
Id EmitSPIRV::EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
- return ctx.OpSLessThan(ctx.u1, lhs, rhs);
+ return ctx.OpSLessThan(ctx.U1, lhs, rhs);
}
void EmitSPIRV::EmitULessThan(EmitContext&) {
@@ -94,7 +94,7 @@ void EmitSPIRV::EmitULessThanEqual(EmitContext&) {
}
Id EmitSPIRV::EmitSGreaterThan(EmitContext& ctx, Id lhs, Id rhs) {
- return ctx.OpSGreaterThan(ctx.u1, lhs, rhs);
+ return ctx.OpSGreaterThan(ctx.U1, lhs, rhs);
}
void EmitSPIRV::EmitUGreaterThan(EmitContext&) {
@@ -110,7 +110,7 @@ void EmitSPIRV::EmitSGreaterThanEqual(EmitContext&) {
}
Id EmitSPIRV::EmitUGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs) {
- return ctx.OpUGreaterThanEqual(ctx.u1, lhs, rhs);
+ return ctx.OpUGreaterThanEqual(ctx.U1, lhs, rhs);
}
void EmitSPIRV::EmitLogicalOr(EmitContext&) {