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authorChin <chin.bimbo@gmail.com>2015-01-04 19:59:34 +0100
committerchinhodado <chin.bimbo@gmail.com>2015-01-19 22:01:06 +0100
commitfa8e6272c8c080b41a809eb064ab5ba6c8680b1e (patch)
treecde74447bf04d5293810043e74c8e5e767e4a892 /src/core
parentMerge pull request #383 from zhuowei/shared_page (diff)
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Diffstat (limited to 'src/core')
-rw-r--r--src/core/arm/interpreter/armemu.cpp57
-rw-r--r--src/core/arm/skyeye_common/vfp/vfp.cpp155
-rw-r--r--src/core/arm/skyeye_common/vfp/vfp.h11
-rw-r--r--src/core/arm/skyeye_common/vfp/vfpdouble.cpp85
-rw-r--r--src/core/arm/skyeye_common/vfp/vfpinstr.cpp332
5 files changed, 157 insertions, 483 deletions
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index 12166bf79..adc5c3a05 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -340,7 +340,6 @@ ARMword ARMul_Debug(ARMul_State * state, ARMword pc, ARMword instr)
mem_Dbugdump();
}*/
-
/*if (pc == 0x0022D168)
{
int j = 0;
@@ -1117,7 +1116,6 @@ ARMul_Emulate26 (ARMul_State * state)
//chy 2003-08-24 now #if 0 .... #endif process cp14, cp15.reg14, I disable it...
-
/* Actual execution of instructions begins here. */
/* If the condition codes don't match, stop here. */
if (temp) {
@@ -1178,8 +1176,6 @@ mainswitch:
tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb));
dst = ((data >> msb) << (msb - lsb));
dst = (dst << lsb) | tmp_rd;
- /*SKYEYE_DBG("BFC instr: msb = %d, lsb = %d, Rd[%d] : 0x%x, dst = 0x%x\n",
- msb, lsb, Rd, state->Reg[Rd], dst);*/
goto donext;
} // bfc instr
else if (((msb >= lsb) && (msb < 32))) {
@@ -1189,8 +1185,6 @@ mainswitch:
tmp_rd = ((ARMword)(data << (31 - lsb)) >> (31 - lsb));
dst = ((data >> msb) << (msb - lsb)) | tmp_rn;
dst = (dst << lsb) | tmp_rd;
- /*SKYEYE_DBG("BFI instr:msb = %d, lsb = %d, Rd[%d] : 0x%x, Rn[%d]: 0x%x, dst = 0x%x\n",
- msb, lsb, Rd, state->Reg[Rd], Rn, state->Reg[Rn], dst);*/
goto donext;
} // bfi instr
}
@@ -2215,10 +2209,8 @@ mainswitch:
state->currentexvald == (u32)ARMul_ReadWord(state, state->currentexaddr + 4))
enter = true;
-
//todo bug this and STREXD and LDREXD http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360e/CHDGJGGC.html
-
if (enter) {
ARMul_StoreWordN(state, LHS, state->Reg[RHSReg]);
ARMul_StoreWordN(state,LHS + 4 , state->Reg[RHSReg + 1]);
@@ -2254,9 +2246,6 @@ mainswitch:
LHPREUPWB ();
/* Continue with remaining instruction decoding. */
-
-
-
#endif
dest = DPSRegRHS;
WRITESDEST (dest);
@@ -2296,7 +2285,6 @@ mainswitch:
temp = LHS + GetLS7RHS (state, instr);
LoadHalfWord (state, instr, temp, LSIGNED);
break;
-
}
if (BITS (4, 7) == 0xb) {
/* LDRH immediate offset, no write-back, up, pre indexed. */
@@ -2321,7 +2309,6 @@ mainswitch:
}
/* LDR immediate offset, no write-back, up, pre indexed. */
LHPREUP ();
-
}
#endif
@@ -2342,7 +2329,6 @@ mainswitch:
if (state->currentexval == (u32)ARMul_LoadHalfWord(state, state->currentexaddr))enter = true;
-
//StoreWord(state, lhs, RHS)
if (state->Aborted) {
TAKEABORT;
@@ -2396,7 +2382,6 @@ mainswitch:
WRITESDEST (dest);
break;
-
/* Data Processing Immediate RHS Instructions. */
case 0x20: /* AND immed */
@@ -2553,8 +2538,6 @@ mainswitch:
dest = BITS(16, 19);
dest = ((dest<<12) | BITS(0, 11));
WRITEDEST(dest);
- //SKYEYE_DBG("In %s, line = %d, pc = 0x%x, instr = 0x%x, R[0:11]: 0x%x, R[16:19]: 0x%x, R[%d]:0x%x\n",
- // __func__, __LINE__, pc, instr, BITS(0, 11), BITS(16, 19), DESTReg, state->Reg[DESTReg]);
break;
} else {
UNDEF_Test;
@@ -2717,7 +2700,6 @@ mainswitch:
WRITESDEST (~rhs);
break;
-
/* Single Data Transfer Immediate RHS Instructions. */
case 0x40: /* Store Word, No WriteBack, Post Dec, Immed. */
@@ -2849,7 +2831,6 @@ mainswitch:
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
break;
-
case 0x50: /* Store Word, No WriteBack, Pre Dec, Immed. */
(void) StoreWord (state, instr, LHS - LSImmRHS);
break;
@@ -2946,7 +2927,6 @@ mainswitch:
LSBase = temp;
break;
-
/* Single Data Transfer Register RHS Instructions. */
case 0x60: /* Store Word, No WriteBack, Post Dec, Reg. */
@@ -3234,11 +3214,9 @@ mainswitch:
int Rm = 0;
/* utxb */
if (BITS(15, 19) == 0xf && BITS(4, 7) == 0x7) {
-
Rm = (RHS >> (8 * BITS(10, 11))) & 0xff;
DEST = Rm;
}
-
}
#endif
if (BIT (4)) {
@@ -3285,7 +3263,6 @@ mainswitch:
state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
break;
-
case 0x70: /* Store Word, No WriteBack, Pre Dec, Reg. */
if (BIT (4)) {
#ifdef MODE32
@@ -3489,7 +3466,6 @@ mainswitch:
LSBase = temp;
break;
-
/* Multiple Data Transfer Instructions. */
case 0x80: /* Store, No WriteBack, Post Dec. */
@@ -3636,7 +3612,6 @@ mainswitch:
LOADSMULT (instr, temp + 4L, temp + LSMNumRegs);
break;
-
/* Branch forward. */
case 0xa0:
case 0xa1:
@@ -3650,7 +3625,6 @@ mainswitch:
FLUSHPIPE;
break;
-
/* Branch backward. */
case 0xa8:
case 0xa9:
@@ -3664,7 +3638,6 @@ mainswitch:
FLUSHPIPE;
break;
-
/* Branch and Link forward. */
case 0xb0:
case 0xb1:
@@ -3690,10 +3663,8 @@ mainswitch:
printf("call %08X %08X %s(%08X %08X %08X %08X %08X %08X %08X)\n", state->Reg[14], state->Reg[15], a, state->Reg[0], state->Reg[1], state->Reg[2], state->Reg[3], mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] - 4),mem_Read32(state->Reg[13] - 8));
#endif
-
break;
-
/* Branch and Link backward. */
case 0xb8:
case 0xb9:
@@ -3712,18 +3683,14 @@ mainswitch:
state->Reg[15] = pc + 8 + NEGBRANCH;
FLUSHPIPE;
-
#ifdef callstacker
memset(a, 0, 256);
aufloeser(a, state->Reg[15]);
printf("call %08X %08X %s(%08X %08X %08X %08X %08X %08X %08X)\n", state->Reg[14], state->Reg[15], a, state->Reg[0], state->Reg[1], state->Reg[2], state->Reg[3], mem_Read32(state->Reg[13]), mem_Read32(state->Reg[13] - 4),mem_Read32(state->Reg[13] - 8));
#endif
-
-
break;
-
/* Co-Processor Data Transfers. */
case 0xc4:
if ((instr & 0x0FF00FF0) == 0xC400B10) { //vmov BIT(0-3), BIT(12-15), BIT(16-20), vmov d0, r0, r0
@@ -3859,7 +3826,6 @@ mainswitch:
ARMul_LDC (state, instr, lhs);
break;
-
/* Co-Processor Register Transfers (MCR) and Data Ops. */
case 0xe2:
@@ -3891,7 +3857,6 @@ mainswitch:
ARMul_CDP (state, instr);
break;
-
/* Co-Processor Register Transfers (MRC) and Data Ops. */
case 0xe1:
case 0xe3:
@@ -3916,7 +3881,6 @@ mainswitch:
ARMul_CDP (state, instr);
break;
-
/* SWI instruction. */
case 0xf0:
case 0xf1:
@@ -3936,7 +3900,7 @@ mainswitch:
case 0xff:
//svc_Execute(state, BITS(0, 23));
HLE::CallSVC(instr);
-
+
break;
}
}
@@ -4118,7 +4082,6 @@ TEST_EMULATE:
// continue;
else if (state->Emulate != RUN)
break;
-
}
while (state->NumInstrsToExecute);
@@ -4156,7 +4119,6 @@ exit:
static FILE *fd;
/*if (!init) {
-
fd = fopen("./pc.txt", "w");
if (!fd) {
exit(-1);
@@ -4725,8 +4687,6 @@ out:
address, DEST); \
}
-
-
static unsigned
LoadWord (ARMul_State * state, ARMword instr, ARMword address) {
ARMword dest;
@@ -5158,7 +5118,6 @@ out:
/*chy 2004-05-23 chy goto end */
if (state->Aborted)
goto L_ldm_makeabort;
-
}
if (BIT (15) && !state->Aborted)
@@ -5202,7 +5161,6 @@ L_ldm_makeabort:
LSBase = WBBase;
}
/* chy 2005-11-24, over */
-
}
/* This function does the work of loading the registers listed in an LDM
@@ -5405,7 +5363,6 @@ L_ldm_s_makeabort:
//chy 2004-05-23, needn't store other when aborted
if (state->Aborted)
goto L_stm_takeabort;
-
}
//chy 2004-05-23,should compare the Abort Models
@@ -5508,7 +5465,6 @@ L_stm_takeabort:
/* Restore the correct bank. */
(void) ARMul_SwitchMode (state, USER26MODE, state->Mode);
-
//chy 2004-05-23,should compare the Abort Models
L_stm_s_takeabort:
if (BIT (21) && LHSReg != 15) {
@@ -5763,7 +5719,6 @@ L_stm_s_takeabort:
TAKEABORT;
}
-
if (enter) {
ARMul_StoreByte(state, lhs, RHS);
state->Reg[DESTReg] = 0;
@@ -6285,7 +6240,7 @@ L_stm_s_takeabort:
u32 rm = ((state->Reg[BITS(0, 3)] >> rotation) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - rotation)) & 0xFF) & 0xFF);
if (rm & 0x80)
rm |= 0xffffff00;
-
+
// SXTB, otherwise SXTAB
if (BITS(16, 19) == 0xf)
state->Reg[BITS(12, 15)] = rm;
@@ -6371,7 +6326,7 @@ L_stm_s_takeabort:
const s16 max = 0xFFFF >> (16 - num_bits);
s16 rn_lo = (state->Reg[rn_idx]);
s16 rn_hi = (state->Reg[rn_idx] >> 16);
-
+
if (max < rn_lo) {
rn_lo = max;
SETQ;
@@ -6379,7 +6334,7 @@ L_stm_s_takeabort:
rn_lo = 0;
SETQ;
}
-
+
if (max < rn_hi) {
rn_hi = max;
SETQ;
@@ -6387,14 +6342,14 @@ L_stm_s_takeabort:
rn_hi = 0;
SETQ;
}
-
+
state->Reg[rd_idx] = (rn_lo & 0xFFFF) | ((rn_hi << 16) & 0xFFFF);
return 1;
}
else if (op2 == 0x03) {
const u8 rotate = BITS(10, 11) * 8;
const u32 rm = ((state->Reg[BITS(0, 3)] >> rotate) & 0xFF) | (((state->Reg[BITS(0, 3)] << (32 - rotate)) & 0xFF) & 0xFF);
-
+
if (BITS(16, 19) == 0xf)
/* UXTB */
state->Reg[BITS(12, 15)] = rm;
diff --git a/src/core/arm/skyeye_common/vfp/vfp.cpp b/src/core/arm/skyeye_common/vfp/vfp.cpp
index 10d640f37..62a2f63ca 100644
--- a/src/core/arm/skyeye_common/vfp/vfp.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfp.cpp
@@ -20,16 +20,11 @@
/* Note: this file handles interface with arm core and vfp registers */
-/* Opens debug for classic interpreter only */
-//#define DEBUG
-
#include "common/common.h"
#include "core/arm/skyeye_common/armdefs.h"
#include "core/arm/skyeye_common/vfp/vfp.h"
-#define DEBUG DBG
-
//ARMul_State* persistent_state; /* function calls from SoftFloat lib don't have an access to ARMul_state. */
unsigned VFPInit(ARMul_State* state)
@@ -75,7 +70,7 @@ unsigned VFPMRC(ARMul_State* state, unsigned type, u32 instr, u32* value)
return ARMul_DONE;
}
}
- DEBUG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n",
+ LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n",
instr, CoProc, OPC_1, Rt, CRn, CRm, OPC_2);
return ARMul_CANT;
@@ -122,7 +117,7 @@ unsigned VFPMCR(ARMul_State* state, unsigned type, u32 instr, u32 value)
return ARMul_DONE;
}
}
- DEBUG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n",
+ LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, CRn %x, CRm %x, OPC_2 %x\n",
instr, CoProc, OPC_1, Rt, CRn, CRm, OPC_2);
return ARMul_CANT;
@@ -152,7 +147,7 @@ unsigned VFPMRRC(ARMul_State* state, unsigned type, u32 instr, u32* value1, u32*
return ARMul_DONE;
}
}
- DEBUG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n",
+ LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n",
instr, CoProc, OPC_1, Rt, Rt2, CRm);
return ARMul_CANT;
@@ -186,7 +181,7 @@ unsigned VFPMCRR(ARMul_State* state, unsigned type, u32 instr, u32 value1, u32 v
return ARMul_DONE;
}
}
- DEBUG("Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n",
+ LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, OPC_1 %x, Rt %x, Rt2 %x, CRm %x\n",
instr, CoProc, OPC_1, Rt, Rt2, CRm);
return ARMul_CANT;
@@ -208,17 +203,17 @@ unsigned VFPSTC(ARMul_State* state, unsigned type, u32 instr, u32 * value)
/* VSTM */
if ( (P|U|D|W) == 0 ) {
- DEBUG("In %s, UNDEFINED\n", __FUNCTION__);
+ LOG_ERROR(Core_ARM11, "In %s, UNDEFINED\n", __FUNCTION__);
exit(-1);
}
if (CoProc == 10 || CoProc == 11) {
#if 1
if (P == 0 && U == 0 && W == 0) {
- DEBUG("VSTM Related encodings\n");
+ LOG_ERROR(Core_ARM11, "VSTM Related encodings\n");
exit(-1);
}
if (P == U && W == 1) {
- DEBUG("UNDEFINED\n");
+ LOG_ERROR(Core_ARM11, "UNDEFINED\n");
exit(-1);
}
#endif
@@ -235,7 +230,7 @@ unsigned VFPSTC(ARMul_State* state, unsigned type, u32 instr, u32 * value)
return VSTM(state, type, instr, value);
}
- DEBUG("Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n",
+ LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n",
instr, CoProc, CRd, Rn, imm8, P, U, D, W);
return ARMul_CANT;
@@ -256,7 +251,7 @@ unsigned VFPLDC(ARMul_State* state, unsigned type, u32 instr, u32 value)
/* TODO check access permission */
if ( (P|U|D|W) == 0 ) {
- DEBUG("In %s, UNDEFINED\n", __FUNCTION__);
+ LOG_ERROR(Core_ARM11, "In %s, UNDEFINED\n", __FUNCTION__);
exit(-1);
}
if (CoProc == 10 || CoProc == 11)
@@ -273,7 +268,7 @@ unsigned VFPLDC(ARMul_State* state, unsigned type, u32 instr, u32 value)
return VLDM(state, type, instr, value);
}
- DEBUG("Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n",
+ LOG_WARNING(Core_ARM11, "Can't identify %x, CoProc %x, CRd %x, Rn %x, imm8 %x, P %x, U %x, D %x, W %x\n",
instr, CoProc, CRd, Rn, imm8, P, U, D, W);
return ARMul_CANT;
@@ -340,33 +335,6 @@ unsigned VFPCDP(ARMul_State* state, unsigned type, u32 instr)
if (CoProc == 10 || CoProc == 11)
{
- if ((OPC_1 & 0xB) == 0 && (OPC_2 & 0x2) == 0)
- DBG("VMLA :\n");
-
- if ((OPC_1 & 0xB) == 0 && (OPC_2 & 0x2) == 2)
- DBG("VMLS :\n");
-
- if ((OPC_1 & 0xB) == 1 && (OPC_2 & 0x2) == 2)
- DBG("VNMLA :\n");
-
- if ((OPC_1 & 0xB) == 1 && (OPC_2 & 0x2) == 0)
- DBG("VNMLS :\n");
-
- if ((OPC_1 & 0xB) == 2 && (OPC_2 & 0x2) == 2)
- DBG("VNMUL :\n");
-
- if ((OPC_1 & 0xB) == 2 && (OPC_2 & 0x2) == 0)
- DBG("VMUL :\n");
-
- if ((OPC_1 & 0xB) == 3 && (OPC_2 & 0x2) == 0)
- DBG("VADD :\n");
-
- if ((OPC_1 & 0xB) == 3 && (OPC_2 & 0x2) == 2)
- DBG("VSUB :\n");
-
- if ((OPC_1 & 0xB) == 0xA && (OPC_2 & 0x2) == 0)
- DBG("VDIV :\n");
-
if ((OPC_1 & 0xB) == 0xB && BITS(4, 7) == 0)
{
unsigned int single = BIT(8) == 0;
@@ -392,30 +360,6 @@ unsigned VFPCDP(ARMul_State* state, unsigned type, u32 instr)
return ARMul_DONE;
}
- if ((OPC_1 & 0xB) == 0xB && CRn == 0 && (OPC_2 & 0x7) == 6)
- DBG("VABS :\n");
-
- if ((OPC_1 & 0xB) == 0xB && CRn == 1 && (OPC_2 & 0x7) == 2)
- DBG("VNEG :\n");
-
- if ((OPC_1 & 0xB) == 0xB && CRn == 1 && (OPC_2 & 0x7) == 6)
- DBG("VSQRT :\n");
-
- if ((OPC_1 & 0xB) == 0xB && CRn == 4 && (OPC_2 & 0x2) == 2)
- DBG("VCMP(1) :\n");
-
- if ((OPC_1 & 0xB) == 0xB && CRn == 5 && (OPC_2 & 0x2) == 2 && CRm == 0)
- DBG("VCMP(2) :\n");
-
- if ((OPC_1 & 0xB) == 0xB && CRn == 7 && (OPC_2 & 0x6) == 6)
- DBG("VCVT(BDS) :\n");
-
- if ((OPC_1 & 0xB) == 0xB && CRn >= 0xA && (OPC_2 & 0x2) == 2)
- DBG("VCVT(BFF) :\n");
-
- if ((OPC_1 & 0xB) == 0xB && CRn > 7 && (OPC_2 & 0x2) == 2)
- DBG("VCVT(BFI) :\n");
-
int exceptions = 0;
if (CoProc == 10)
exceptions = vfp_single_cpdo(state, instr, state->VFP[VFP_OFFSET(VFP_FPSCR)]);
@@ -426,40 +370,33 @@ unsigned VFPCDP(ARMul_State* state, unsigned type, u32 instr)
return ARMul_DONE;
}
- DEBUG("Can't identify %x\n", instr);
+ LOG_WARNING(Core_ARM11, "Can't identify %x\n", instr);
return ARMul_CANT;
}
-
/* ----------- MRC ------------ */
void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword* value)
{
- DBG("VMOV(BRS) :\n");
if (to_arm)
{
- DBG("\tr%d <= s%d=[%x]\n", t, n, state->ExtReg[n]);
*value = state->ExtReg[n];
}
else
{
- DBG("\ts%d <= r%d=[%x]\n", n, t, *value);
state->ExtReg[n] = *value;
}
}
void VMRS(ARMul_State* state, ARMword reg, ARMword Rt, ARMword* value)
{
- DBG("VMRS :");
if (reg == 1)
{
if (Rt != 15)
{
*value = state->VFP[VFP_OFFSET(VFP_FPSCR)];
- DBG("\tr%d <= fpscr[%08x]\n", Rt, state->VFP[VFP_OFFSET(VFP_FPSCR)]);
}
else
{
*value = state->VFP[VFP_OFFSET(VFP_FPSCR)] ;
- DBG("\tflags <= fpscr[%1xxxxxxxx]\n", state->VFP[VFP_OFFSET(VFP_FPSCR)]>>28);
}
}
else
@@ -468,54 +405,46 @@ void VMRS(ARMul_State* state, ARMword reg, ARMword Rt, ARMword* value)
{
case 0:
*value = state->VFP[VFP_OFFSET(VFP_FPSID)];
- DBG("\tr%d <= fpsid[%08x]\n", Rt, state->VFP[VFP_OFFSET(VFP_FPSID)]);
break;
case 6:
/* MVFR1, VFPv3 only ? */
- DBG("\tr%d <= MVFR1 unimplemented\n", Rt);
+ LOG_TRACE(Core_ARM11, "\tr%d <= MVFR1 unimplemented\n", Rt);
break;
case 7:
/* MVFR0, VFPv3 only? */
- DBG("\tr%d <= MVFR0 unimplemented\n", Rt);
+ LOG_TRACE(Core_ARM11, "\tr%d <= MVFR0 unimplemented\n", Rt);
break;
case 8:
*value = state->VFP[VFP_OFFSET(VFP_FPEXC)];
- DBG("\tr%d <= fpexc[%08x]\n", Rt, state->VFP[VFP_OFFSET(VFP_FPEXC)]);
break;
default:
- DBG("\tSUBARCHITECTURE DEFINED\n");
+ LOG_TRACE(Core_ARM11, "\tSUBARCHITECTURE DEFINED\n");
break;
}
}
}
void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2)
{
- DBG("VMOV(BRRD) :\n");
if (to_arm)
{
- DBG("\tr[%d-%d] <= s[%d-%d]=[%x-%x]\n", t2, t, n*2+1, n*2, state->ExtReg[n*2+1], state->ExtReg[n*2]);
*value2 = state->ExtReg[n*2+1];
*value1 = state->ExtReg[n*2];
}
else
{
- DBG("\ts[%d-%d] <= r[%d-%d]=[%x-%x]\n", n*2+1, n*2, t2, t, *value2, *value1);
state->ExtReg[n*2+1] = *value2;
state->ExtReg[n*2] = *value1;
}
}
void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2)
{
- DBG("VMOV(BRRSS) :\n");
if (to_arm)
{
- DBG("\tr[%d-%d] <= s[%d-%d]=[%x-%x]\n", t2, t, n+1, n, state->ExtReg[n+1], state->ExtReg[n]);
*value1 = state->ExtReg[n+0];
*value2 = state->ExtReg[n+1];
}
else
{
- DBG("\ts[%d-%d] <= r[%d-%d]=[%x-%x]\n", n+1, n, t2, t, *value2, *value1);
state->ExtReg[n+0] = *value1;
state->ExtReg[n+1] = *value2;
}
@@ -526,12 +455,10 @@ void VMSR(ARMul_State* state, ARMword reg, ARMword Rt)
{
if (reg == 1)
{
- DBG("VMSR :\tfpscr <= r%d=[%x]\n", Rt, state->Reg[Rt]);
state->VFP[VFP_OFFSET(VFP_FPSCR)] = state->Reg[Rt];
}
else if (reg == 8)
{
- DBG("VMSR :\tfpexc <= r%d=[%x]\n", Rt, state->Reg[Rt]);
state->VFP[VFP_OFFSET(VFP_FPEXC)] = state->Reg[Rt];
}
}
@@ -556,8 +483,6 @@ int VSTR(ARMul_State* state, int type, ARMword instr, ARMword* value)
d = single_reg ? BITS(12, 15)<<1|BIT(22) : BIT(22)<<4|BITS(12, 15); /* Base register */
n = BITS(16, 19); /* destination register */
- DBG("VSTR :\n");
-
i = 0;
regs = 1;
@@ -568,7 +493,6 @@ int VSTR(ARMul_State* state, int type, ARMword instr, ARMword* value)
if (single_reg)
{
*value = state->ExtReg[d+i];
- DBG("\taddr[?] <= s%d=[%x]\n", d+i, state->ExtReg[d+i]);
i++;
if (i < regs)
return ARMul_INC;
@@ -579,7 +503,6 @@ int VSTR(ARMul_State* state, int type, ARMword instr, ARMword* value)
{
/* FIXME Careful of endianness, may need to rework this */
*value = state->ExtReg[d*2+i];
- DBG("\taddr[?] <= s[%d]=[%x]\n", d*2+i, state->ExtReg[d*2+i]);
i++;
if (i < regs*2)
return ARMul_INC;
@@ -601,10 +524,7 @@ int VPUSH(ARMul_State* state, int type, ARMword instr, ARMword* value)
imm32 = BITS(0,7)<<2; /* may not be used */
regs = single_regs ? BITS(0, 7) : BITS(1, 7); /* FSTMX if regs is odd */
- DBG("VPUSH :\n");
- DBG("\tsp[%x]", state->Reg[R13]);
state->Reg[R13] = state->Reg[R13] - imm32;
- DBG("=>[%x]\n", state->Reg[R13]);
i = 0;
@@ -615,7 +535,6 @@ int VPUSH(ARMul_State* state, int type, ARMword instr, ARMword* value)
if (single_regs)
{
*value = state->ExtReg[d + i];
- DBG("\taddr[?] <= s%d=[%x]\n", d+i, state->ExtReg[d + i]);
i++;
if (i < regs)
return ARMul_INC;
@@ -626,7 +545,6 @@ int VPUSH(ARMul_State* state, int type, ARMword instr, ARMword* value)
{
/* FIXME Careful of endianness, may need to rework this */
*value = state->ExtReg[d*2 + i];
- DBG("\taddr[?] <= s[%d]=[%x]\n", d*2 + i, state->ExtReg[d*2 + i]);
i++;
if (i < regs*2)
return ARMul_INC;
@@ -651,11 +569,8 @@ int VSTM(ARMul_State* state, int type, ARMword instr, ARMword* value)
imm32 = BITS(0,7) * 4; /* may not be used */
regs = single_regs ? BITS(0, 7) : BITS(0, 7)>>1; /* FSTMX if regs is odd */
- DBG("VSTM :\n");
-
if (wback) {
state->Reg[n] = (add ? state->Reg[n] + imm32 : state->Reg[n] - imm32);
- DBG("\twback r%d[%x]\n", n, state->Reg[n]);
}
i = 0;
@@ -667,7 +582,6 @@ int VSTM(ARMul_State* state, int type, ARMword instr, ARMword* value)
if (single_regs)
{
*value = state->ExtReg[d + i];
- DBG("\taddr[?] <= s%d=[%x]\n", d+i, state->ExtReg[d + i]);
i++;
if (i < regs)
return ARMul_INC;
@@ -678,7 +592,6 @@ int VSTM(ARMul_State* state, int type, ARMword instr, ARMword* value)
{
/* FIXME Careful of endianness, may need to rework this */
*value = state->ExtReg[d*2 + i];
- DBG("\taddr[?] <= s[%d]=[%x]\n", d*2 + i, state->ExtReg[d*2 + i]);
i++;
if (i < regs*2)
return ARMul_INC;
@@ -702,10 +615,7 @@ int VPOP(ARMul_State* state, int type, ARMword instr, ARMword value)
imm32 = BITS(0,7)<<2; /* may not be used */
regs = single_regs ? BITS(0, 7) : BITS(1, 7); /* FLDMX if regs is odd */
- DBG("VPOP :\n");
- DBG("\tsp[%x]", state->Reg[R13]);
state->Reg[R13] = state->Reg[R13] + imm32;
- DBG("=>[%x]\n", state->Reg[R13]);
i = 0;
@@ -720,7 +630,6 @@ int VPOP(ARMul_State* state, int type, ARMword instr, ARMword value)
if (single_regs)
{
state->ExtReg[d + i] = value;
- DBG("\ts%d <= [%x]\n", d + i, value);
i++;
if (i < regs)
return ARMul_INC;
@@ -731,7 +640,6 @@ int VPOP(ARMul_State* state, int type, ARMword instr, ARMword value)
{
/* FIXME Careful of endianness, may need to rework this */
state->ExtReg[d*2 + i] = value;
- DBG("\ts%d <= [%x]\n", d*2 + i, value);
i++;
if (i < regs*2)
return ARMul_INC;
@@ -754,11 +662,9 @@ int VLDR(ARMul_State* state, int type, ARMword instr, ARMword value)
d = single_reg ? BITS(12, 15)<<1|BIT(22) : BIT(22)<<4|BITS(12, 15); /* Base register */
n = BITS(16, 19); /* destination register */
- DBG("VLDR :\n");
-
i = 0;
regs = 1;
-
+
return ARMul_DONE;
}
else if (type == ARMul_TRANSFER)
@@ -770,7 +676,6 @@ int VLDR(ARMul_State* state, int type, ARMword instr, ARMword value)
if (single_reg)
{
state->ExtReg[d+i] = value;
- DBG("\ts%d <= [%x]\n", d+i, value);
i++;
if (i < regs)
return ARMul_INC;
@@ -781,7 +686,6 @@ int VLDR(ARMul_State* state, int type, ARMword instr, ARMword value)
{
/* FIXME Careful of endianness, may need to rework this */
state->ExtReg[d*2+i] = value;
- DBG("\ts[%d] <= [%x]\n", d*2+i, value);
i++;
if (i < regs*2)
return ARMul_INC;
@@ -805,12 +709,9 @@ int VLDM(ARMul_State* state, int type, ARMword instr, ARMword value)
n = BITS(16, 19); /* destination register */
imm32 = BITS(0,7) * 4; /* may not be used */
regs = single_regs ? BITS(0, 7) : BITS(0, 7)>>1; /* FLDMX if regs is odd */
-
- DBG("VLDM :\n");
-
+
if (wback) {
state->Reg[n] = (add ? state->Reg[n] + imm32 : state->Reg[n] - imm32);
- DBG("\twback r%d[%x]\n", n, state->Reg[n]);
}
i = 0;
@@ -822,7 +723,6 @@ int VLDM(ARMul_State* state, int type, ARMword instr, ARMword value)
if (single_regs)
{
state->ExtReg[d + i] = value;
- DBG("\ts%d <= [%x] addr[?]\n", d+i, state->ExtReg[d + i]);
i++;
if (i < regs)
return ARMul_INC;
@@ -833,7 +733,6 @@ int VLDM(ARMul_State* state, int type, ARMword instr, ARMword value)
{
/* FIXME Careful of endianness, may need to rework this */
state->ExtReg[d*2 + i] = value;
- DBG("\ts[%d] <= [%x] addr[?]\n", d*2 + i, state->ExtReg[d*2 + i]);
i++;
if (i < regs*2)
return ARMul_INC;
@@ -841,41 +740,33 @@ int VLDM(ARMul_State* state, int type, ARMword instr, ARMword value)
return ARMul_DONE;
}
}
-
+
return -1;
}
/* ----------- CDP ------------ */
void VMOVI(ARMul_State* state, ARMword single, ARMword d, ARMword imm)
{
- DBG("VMOV(I) :\n");
-
if (single)
{
- DBG("\ts%d <= [%x]\n", d, imm);
state->ExtReg[d] = imm;
}
else
{
/* Check endian please */
- DBG("\ts[%d-%d] <= [%x-%x]\n", d*2+1, d*2, imm, 0);
state->ExtReg[d*2+1] = imm;
state->ExtReg[d*2] = 0;
}
}
void VMOVR(ARMul_State* state, ARMword single, ARMword d, ARMword m)
{
- DBG("VMOV(R) :\n");
-
if (single)
{
- DBG("\ts%d <= s%d[%x]\n", d, m, state->ExtReg[m]);
state->ExtReg[d] = state->ExtReg[m];
}
else
{
/* Check endian please */
- DBG("\ts[%d-%d] <= s[%d-%d][%x-%x]\n", d*2+1, d*2, m*2+1, m*2, state->ExtReg[m*2+1], state->ExtReg[m*2]);
state->ExtReg[d*2+1] = state->ExtReg[m*2+1];
state->ExtReg[d*2] = state->ExtReg[m*2];
}
@@ -884,13 +775,13 @@ void VMOVR(ARMul_State* state, ARMword single, ARMword d, ARMword m)
/* Miscellaneous functions */
int32_t vfp_get_float(arm_core_t* state, unsigned int reg)
{
- DEBUG("VFP get float: s%d=[%08x]\n", reg, state->ExtReg[reg]);
+ LOG_TRACE(Core_ARM11, "VFP get float: s%d=[%08x]\n", reg, state->ExtReg[reg]);
return state->ExtReg[reg];
}
void vfp_put_float(arm_core_t* state, int32_t val, unsigned int reg)
{
- DEBUG("VFP put float: s%d <= [%08x]\n", reg, val);
+ LOG_TRACE(Core_ARM11, "VFP put float: s%d <= [%08x]\n", reg, val);
state->ExtReg[reg] = val;
}
@@ -898,13 +789,13 @@ uint64_t vfp_get_double(arm_core_t* state, unsigned int reg)
{
uint64_t result;
result = ((uint64_t) state->ExtReg[reg*2+1])<<32 | state->ExtReg[reg*2];
- DEBUG("VFP get double: s[%d-%d]=[%016llx]\n", reg*2+1, reg*2, result);
+ LOG_TRACE(Core_ARM11, "VFP get double: s[%d-%d]=[%016llx]\n", reg * 2 + 1, reg * 2, result);
return result;
}
void vfp_put_double(arm_core_t* state, uint64_t val, unsigned int reg)
{
- DEBUG("VFP put double: s[%d-%d] <= [%08x-%08x]\n", reg*2+1, reg*2, (uint32_t) (val>>32), (uint32_t) (val & 0xffffffff));
+ LOG_TRACE(Core_ARM11, "VFP put double: s[%d-%d] <= [%08x-%08x]\n", reg * 2 + 1, reg * 2, (uint32_t)(val >> 32), (uint32_t)(val & 0xffffffff));
state->ExtReg[reg*2] = (uint32_t) (val & 0xffffffff);
state->ExtReg[reg*2+1] = (uint32_t) (val>>32);
}
@@ -916,10 +807,10 @@ void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpsc
{
int si_code = 0;
- vfpdebug("VFP: raising exceptions %08x\n", exceptions);
+ LOG_DEBUG(Core_ARM11, "VFP: raising exceptions %08x\n", exceptions);
if (exceptions == VFP_EXCEPTION_ERROR) {
- DEBUG("unhandled bounce %x\n", inst);
+ LOG_TRACE(Core_ARM11, "unhandled bounce %x\n", inst);
exit(-1);
return;
}
diff --git a/src/core/arm/skyeye_common/vfp/vfp.h b/src/core/arm/skyeye_common/vfp/vfp.h
index 539fb0131..5ff213e08 100644
--- a/src/core/arm/skyeye_common/vfp/vfp.h
+++ b/src/core/arm/skyeye_common/vfp/vfp.h
@@ -1,4 +1,4 @@
-/*
+/*
vfp/vfp.h - ARM VFPv3 emulation unit - vfp interface
Copyright (C) 2003 Skyeye Develop Group
for help please send mail to <skyeye-developer@lists.gro.clinux.org>
@@ -21,15 +21,10 @@
#ifndef __VFP_H__
#define __VFP_H__
-#define DBG(...) //DEBUG_LOG(ARM11, __VA_ARGS__)
-
-#define vfpdebug //printf
-
#include "core/arm/skyeye_common/vfp/vfp_helper.h" /* for references to cdp SoftFloat functions */
-#define VFP_DEBUG_TRANSLATE DBG("in func %s, %x\n", __FUNCTION__, inst);
-#define VFP_DEBUG_UNIMPLEMENTED(x) printf("in func %s, " #x " unimplemented\n", __FUNCTION__); exit(-1);
-#define VFP_DEBUG_UNTESTED(x) printf("in func %s, " #x " untested\n", __FUNCTION__);
+#define VFP_DEBUG_UNIMPLEMENTED(x) LOG_ERROR(Core_ARM11, "in func %s, " #x " unimplemented\n", __FUNCTION__); exit(-1);
+#define VFP_DEBUG_UNTESTED(x) LOG_TRACE(Core_ARM11, "in func %s, " #x " untested\n", __FUNCTION__);
#define CHECK_VFP_ENABLED
#define CHECK_VFP_CDP_RET vfp_raise_exceptions(cpu, ret, inst_cream->instr, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]); //if (ret == -1) {printf("VFP CDP FAILURE %x\n", inst_cream->instr); exit(-1);}
diff --git a/src/core/arm/skyeye_common/vfp/vfpdouble.cpp b/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
index a9df490ba..da7de6e65 100644
--- a/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpdouble.cpp
@@ -50,7 +50,7 @@
* this code that are retained.
* ===========================================================================
*/
-
+
#include "core/arm/skyeye_common/vfp/vfp.h"
#include "core/arm/skyeye_common/vfp/vfp_helper.h"
#include "core/arm/skyeye_common/vfp/asm_vfp.h"
@@ -63,7 +63,7 @@ static struct vfp_double vfp_double_default_qnan = {
static void vfp_double_dump(const char *str, struct vfp_double *d)
{
- pr_debug("VFP: %s: sign=%d exponent=%d significand=%016llx\n",
+ LOG_TRACE(Core_ARM11, "VFP: %s: sign=%d exponent=%d significand=%016llx\n",
str, d->sign != 0, d->exponent, d->significand);
}
@@ -155,7 +155,7 @@ u32 vfp_double_normaliseroundintern(ARMul_State* state, struct vfp_double *vd, u
else if ((rmode == FPSCR_ROUND_PLUSINF) ^ (vd->sign != 0))
incr = (1ULL << (VFP_DOUBLE_LOW_BITS + 1)) - 1;
- pr_debug("VFP: rounding increment = 0x%08llx\n", incr);
+ LOG_TRACE(Core_ARM11, "VFP: rounding increment = 0x%08llx\n", incr);
/*
* Is our rounding going to overflow?
@@ -281,7 +281,7 @@ u32 vfp_double_normaliseround(ARMul_State* state, int dd, struct vfp_double *vd,
} else if ((rmode == FPSCR_ROUND_PLUSINF) ^ (vd->sign != 0))
incr = (1ULL << (VFP_DOUBLE_LOW_BITS + 1)) - 1;
- pr_debug("VFP: rounding increment = 0x%08llx\n", incr);
+ LOG_TRACE(Core_ARM11, "VFP: rounding increment = 0x%08llx\n", incr);
/*
* Is our rounding going to overflow?
@@ -336,7 +336,7 @@ pack:
vfp_double_dump("pack: final", vd);
{
s64 d = vfp_double_pack(vd);
- pr_debug("VFP: %s: d(d%d)=%016llx exceptions=%08x\n", func,
+ LOG_TRACE(Core_ARM11, "VFP: %s: d(d%d)=%016llx exceptions=%08x\n", func,
dd, d, exceptions);
vfp_put_double(state, d, dd);
}
@@ -393,28 +393,28 @@ vfp_propagate_nan(struct vfp_double *vdd, struct vfp_double *vdn,
*/
static u32 vfp_double_fabs(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_put_double(state, vfp_double_packed_abs(vfp_get_double(state, dm)), dd);
return 0;
}
static u32 vfp_double_fcpy(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_put_double(state, vfp_get_double(state, dm), dd);
return 0;
}
static u32 vfp_double_fneg(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_put_double(state, vfp_double_packed_negate(vfp_get_double(state, dm)), dd);
return 0;
}
static u32 vfp_double_fsqrt(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_double vdm, vdd, *vdp;
int ret, tm;
@@ -508,7 +508,7 @@ static u32 vfp_compare(ARMul_State* state, int dd, int signal_on_qnan, int dm, u
s64 d, m;
u32 ret = 0;
- pr_debug("In %s, state=0x%x, fpscr=0x%x\n", __FUNCTION__, state, fpscr);
+ LOG_TRACE(Core_ARM11, "In %s, state=0x%x, fpscr=0x%x\n", __FUNCTION__, state, fpscr);
m = vfp_get_double(state, dm);
if (vfp_double_packed_exponent(m) == 2047 && vfp_double_packed_mantissa(m)) {
ret |= FPSCR_C | FPSCR_V;
@@ -563,32 +563,32 @@ static u32 vfp_compare(ARMul_State* state, int dd, int signal_on_qnan, int dm, u
ret |= FPSCR_C;
}
}
- pr_debug("In %s, state=0x%x, ret=0x%x\n", __FUNCTION__, state, ret);
+ LOG_TRACE(Core_ARM11, "In %s, state=0x%x, ret=0x%x\n", __FUNCTION__, state, ret);
return ret;
}
static u32 vfp_double_fcmp(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
return vfp_compare(state, dd, 0, dm, fpscr);
}
static u32 vfp_double_fcmpe(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
return vfp_compare(state, dd, 1, dm, fpscr);
}
static u32 vfp_double_fcmpz(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
return vfp_compare(state, dd, 0, VFP_REG_ZERO, fpscr);
}
static u32 vfp_double_fcmpez(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
return vfp_compare(state, dd, 1, VFP_REG_ZERO, fpscr);
}
@@ -598,7 +598,7 @@ u32 vfp_double_fcvtsinterncutting(ARMul_State* state, int sd, struct vfp_double*
int tm;
u32 exceptions = 0;
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
tm = vfp_double_type(dm);
@@ -642,7 +642,7 @@ static u32 vfp_double_fcvts(ARMul_State* state, int sd, int unused, int dm, u32
int tm;
u32 exceptions = 0;
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_double_unpack(&vdm, vfp_get_double(state, dm));
tm = vfp_double_type(&vdm);
@@ -684,7 +684,7 @@ static u32 vfp_double_fuito(ARMul_State* state, int dd, int unused, int dm, u32
struct vfp_double vdm;
u32 m = vfp_get_float(state, dm);
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vdm.sign = 0;
vdm.exponent = 1023 + 63 - 1;
vdm.significand = (u64)m;
@@ -697,7 +697,7 @@ static u32 vfp_double_fsito(ARMul_State* state, int dd, int unused, int dm, u32
struct vfp_double vdm;
u32 m = vfp_get_float(state, dm);
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vdm.sign = (m & 0x80000000) >> 16;
vdm.exponent = 1023 + 63 - 1;
vdm.significand = vdm.sign ? -m : m;
@@ -712,7 +712,7 @@ static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32
int rmode = fpscr & FPSCR_RMODE_MASK;
int tm;
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_double_unpack(&vdm, vfp_get_double(state, dm));
/*
@@ -773,7 +773,7 @@ static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32
}
}
- pr_debug("VFP: ftoui: d(s%d)=%08x exceptions=%08x\n", sd, d, exceptions);
+ LOG_TRACE(Core_ARM11, "VFP: ftoui: d(s%d)=%08x exceptions=%08x\n", sd, d, exceptions);
vfp_put_float(state, d, sd);
@@ -782,7 +782,7 @@ static u32 vfp_double_ftoui(ARMul_State* state, int sd, int unused, int dm, u32
static u32 vfp_double_ftouiz(ARMul_State* state, int sd, int unused, int dm, u32 fpscr)
{
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
return vfp_double_ftoui(state, sd, unused, dm, FPSCR_ROUND_TOZERO);
}
@@ -793,7 +793,7 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32
int rmode = fpscr & FPSCR_RMODE_MASK;
int tm;
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_double_unpack(&vdm, vfp_get_double(state, dm));
vfp_double_dump("VDM", &vdm);
@@ -850,7 +850,7 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32
}
}
- pr_debug("VFP: ftosi: d(s%d)=%08x exceptions=%08x\n", sd, d, exceptions);
+ LOG_TRACE(Core_ARM11, "VFP: ftosi: d(s%d)=%08x exceptions=%08x\n", sd, d, exceptions);
vfp_put_float(state, (s32)d, sd);
@@ -859,7 +859,7 @@ static u32 vfp_double_ftosi(ARMul_State* state, int sd, int unused, int dm, u32
static u32 vfp_double_ftosiz(ARMul_State* state, int dd, int unused, int dm, u32 fpscr)
{
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
return vfp_double_ftosi(state, dd, unused, dm, FPSCR_ROUND_TOZERO);
}
@@ -894,9 +894,6 @@ static struct op fops_ext[] = {
{ vfp_double_ftosiz, OP_SCALAR }, //0x0000001B - FEXT_FTOSIZ
};
-
-
-
static u32
vfp_double_fadd_nonnumber(struct vfp_double *vdd, struct vfp_double *vdn,
struct vfp_double *vdm, u32 fpscr)
@@ -946,7 +943,7 @@ u32 vfp_double_add(struct vfp_double *vdd, struct vfp_double *vdn,struct vfp_dou
if (vdn->significand & (1ULL << 63) ||
vdm->significand & (1ULL << 63)) {
- pr_info("VFP: bad FP values in %s\n", __func__);
+ LOG_INFO(Core_ARM11, "VFP: bad FP values in %s\n", __func__);
vfp_double_dump("VDN", vdn);
vfp_double_dump("VDM", vdm);
}
@@ -1018,7 +1015,7 @@ vfp_double_multiply(struct vfp_double *vdd, struct vfp_double *vdn,
struct vfp_double *t = vdn;
vdn = vdm;
vdm = t;
- pr_debug("VFP: swapping M <-> N\n");
+ LOG_TRACE(Core_ARM11, "VFP: swapping M <-> N\n");
}
vdd->sign = vdn->sign ^ vdm->sign;
@@ -1099,7 +1096,7 @@ vfp_double_multiply_accumulate(ARMul_State* state, int dd, int dn, int dm, u32 f
*/
static u32 vfp_double_fmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr)
{
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, 0, "fmac");
}
@@ -1108,7 +1105,7 @@ static u32 vfp_double_fmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
*/
static u32 vfp_double_fnmac(ARMul_State* state, int dd, int dn, int dm, u32 fpscr)
{
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_MULTIPLY, "fnmac");
}
@@ -1117,7 +1114,7 @@ static u32 vfp_double_fnmac(ARMul_State* state, int dd, int dn, int dm, u32 fpsc
*/
static u32 vfp_double_fmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr)
{
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_SUBTRACT, "fmsc");
}
@@ -1126,7 +1123,7 @@ static u32 vfp_double_fmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
*/
static u32 vfp_double_fnmsc(ARMul_State* state, int dd, int dn, int dm, u32 fpscr)
{
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
return vfp_double_multiply_accumulate(state, dd, dn, dm, fpscr, NEG_SUBTRACT | NEG_MULTIPLY, "fnmsc");
}
@@ -1138,7 +1135,7 @@ static u32 vfp_double_fmul(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
struct vfp_double vdd, vdn, vdm;
u32 exceptions;
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_double_unpack(&vdn, vfp_get_double(state, dn));
if (vdn.exponent == 0 && vdn.significand)
vfp_double_normalise_denormal(&vdn);
@@ -1159,7 +1156,7 @@ static u32 vfp_double_fnmul(ARMul_State* state, int dd, int dn, int dm, u32 fpsc
struct vfp_double vdd, vdn, vdm;
u32 exceptions;
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_double_unpack(&vdn, vfp_get_double(state, dn));
if (vdn.exponent == 0 && vdn.significand)
vfp_double_normalise_denormal(&vdn);
@@ -1182,7 +1179,7 @@ static u32 vfp_double_fadd(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
struct vfp_double vdd, vdn, vdm;
u32 exceptions;
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_double_unpack(&vdn, vfp_get_double(state, dn));
if (vdn.exponent == 0 && vdn.significand)
vfp_double_normalise_denormal(&vdn);
@@ -1204,7 +1201,7 @@ static u32 vfp_double_fsub(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
struct vfp_double vdd, vdn, vdm;
u32 exceptions;
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_double_unpack(&vdn, vfp_get_double(state, dn));
if (vdn.exponent == 0 && vdn.significand)
vfp_double_normalise_denormal(&vdn);
@@ -1232,7 +1229,7 @@ static u32 vfp_double_fdiv(ARMul_State* state, int dd, int dn, int dm, u32 fpscr
u32 exceptions = 0;
int tm, tn;
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vfp_double_unpack(&vdn, vfp_get_double(state, dn));
vfp_double_unpack(&vdm, vfp_get_double(state, dm));
@@ -1357,7 +1354,7 @@ u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr)
unsigned int vecitr, veclen, vecstride;
struct op *fop;
- pr_debug("In %s\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "In %s\n", __FUNCTION__);
vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK));
fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)];
@@ -1388,7 +1385,7 @@ u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr)
else
veclen = fpscr & FPSCR_LENGTH_MASK;
- pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride,
+ LOG_TRACE(Core_ARM11, "VFP: vecstride=%u veclen=%u\n", vecstride,
(veclen >> FPSCR_LENGTH_BIT) + 1);
if (!fop->fn) {
@@ -1402,16 +1399,16 @@ u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr)
type = fop->flags & OP_SD ? 's' : 'd';
if (op == FOP_EXT)
- pr_debug("VFP: itr%d (%c%u) = op[%u] (d%u)\n",
+ LOG_TRACE(Core_ARM11, "VFP: itr%d (%c%u) = op[%u] (d%u)\n",
vecitr >> FPSCR_LENGTH_BIT,
type, dest, dn, dm);
else
- pr_debug("VFP: itr%d (%c%u) = (d%u) op[%u] (d%u)\n",
+ LOG_TRACE(Core_ARM11, "VFP: itr%d (%c%u) = (d%u) op[%u] (d%u)\n",
vecitr >> FPSCR_LENGTH_BIT,
type, dest, dn, FOP_TO_IDX(op), dm);
except = fop->fn(state, dest, dn, dm, fpscr);
- pr_debug("VFP: itr%d: exceptions=%08x\n",
+ LOG_TRACE(Core_ARM11, "VFP: itr%d: exceptions=%08x\n",
vecitr >> FPSCR_LENGTH_BIT, except);
exceptions |= except;
diff --git a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
index 2c1218c30..cf459222c 100644
--- a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
@@ -21,8 +21,6 @@ typedef struct _vmla_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vmla)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmla_inst));
vmla_inst *inst_cream = (vmla_inst *)inst_base->component;
@@ -43,8 +41,6 @@ VMLA_INST:
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
- DBG("VMLA :\n");
-
vmla_inst *inst_cream = (vmla_inst *)inst_base->component;
int ret;
@@ -70,7 +66,6 @@ DYNCOM_FILL_ACTION(vmla),
int DYNCOM_TAG(vmla)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
return instr_size;
@@ -78,7 +73,6 @@ int DYNCOM_TAG(vmla)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vmla)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arch_arm_undef(cpu, bb, instr);
int m;
int n;
@@ -124,7 +118,7 @@ int DYNCOM_TRANS(vmla)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
mm = FPBITCAST64(mm);
tmp = FPADD(mm,tmp);
mm = TRUNC32(LSHR(IBITCAST64(tmp),CONST64(32)));
- nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff)));
+ nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff)));
LETFPS(2*d ,FPBITCAST32(nn));
LETFPS(d*2 + 1 , FPBITCAST32(mm));
}
@@ -144,8 +138,6 @@ typedef struct _vmls_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vmls)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmls_inst));
vmls_inst *inst_cream = (vmls_inst *)inst_base->component;
@@ -166,8 +158,6 @@ VMLS_INST:
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
- DBG("VMLS :\n");
-
vmls_inst *inst_cream = (vmls_inst *)inst_base->component;
int ret;
@@ -193,7 +183,6 @@ DYNCOM_FILL_ACTION(vmls),
int DYNCOM_TAG(vmls)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
return instr_size;
@@ -201,7 +190,7 @@ int DYNCOM_TAG(vmls)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vmls)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- DBG("\t\tin %s VMLS instruction is executed out of here.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s VMLS instruction is executed out of here.\n", __FUNCTION__);
//arch_arm_undef(cpu, bb, instr);
int m;
int n;
@@ -247,10 +236,10 @@ int DYNCOM_TRANS(vmls)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
mm = FPBITCAST64(mm);
tmp = FPADD(mm,tmp);
mm = TRUNC32(LSHR(IBITCAST64(tmp),CONST64(32)));
- nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff)));
+ nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff)));
LETFPS(2*d ,FPBITCAST32(nn));
LETFPS(d*2 + 1 , FPBITCAST32(mm));
- }
+ }
return No_exp;
}
#endif
@@ -267,8 +256,6 @@ typedef struct _vnmla_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vnmla)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vnmla_inst));
vnmla_inst *inst_cream = (vnmla_inst *)inst_base->component;
@@ -289,8 +276,6 @@ VNMLA_INST:
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
- DBG("VNMLA :\n");
-
vnmla_inst *inst_cream = (vnmla_inst *)inst_base->component;
int ret;
@@ -317,7 +302,6 @@ DYNCOM_FILL_ACTION(vnmla),
int DYNCOM_TAG(vnmla)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
return instr_size;
@@ -325,7 +309,7 @@ int DYNCOM_TAG(vnmla)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vnmla)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- DBG("\t\tin %s VNMLA instruction is executed out of here.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s VNMLA instruction is executed out of here.\n", __FUNCTION__);
//arch_arm_undef(cpu, bb, instr);
int m;
int n;
@@ -370,7 +354,7 @@ int DYNCOM_TRANS(vnmla)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
mm = OR(SHL(nn,CONST64(32)),mm);
mm = FPBITCAST64(mm);
tmp = FPADD(FPNEG64(mm),tmp);
- mm = TRUNC32(LSHR(IBITCAST64(tmp),CONST64(32)));
+ mm = TRUNC32(LSHR(IBITCAST64(tmp),CONST64(32)));
nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff)));
LETFPS(2*d ,FPBITCAST32(nn));
LETFPS(d*2 + 1 , FPBITCAST32(mm));
@@ -392,8 +376,6 @@ typedef struct _vnmls_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vnmls)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vnmls_inst));
vnmls_inst *inst_cream = (vnmls_inst *)inst_base->component;
@@ -414,8 +396,6 @@ VNMLS_INST:
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
- DBG("VNMLS :\n");
-
vnmls_inst *inst_cream = (vnmls_inst *)inst_base->component;
int ret;
@@ -441,7 +421,7 @@ DYNCOM_FILL_ACTION(vnmls),
int DYNCOM_TAG(vnmls)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
return instr_size;
@@ -449,7 +429,7 @@ int DYNCOM_TAG(vnmls)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vnmls)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arch_arm_undef(cpu, bb, instr);
int m;
int n;
@@ -495,10 +475,10 @@ int DYNCOM_TRANS(vnmls)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
mm = FPBITCAST64(mm);
tmp = FPADD(FPNEG64(mm),tmp);
mm = TRUNC32(LSHR(IBITCAST64(tmp),CONST64(32)));
- nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff)));
+ nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff)));
LETFPS(2*d ,FPBITCAST32(nn));
LETFPS(d*2 + 1 , FPBITCAST32(mm));
- }
+ }
return No_exp;
}
#endif
@@ -515,8 +495,6 @@ typedef struct _vnmul_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vnmul)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vnmul_inst));
vnmul_inst *inst_cream = (vnmul_inst *)inst_base->component;
@@ -537,8 +515,6 @@ VNMUL_INST:
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
- DBG("VNMUL :\n");
-
vnmul_inst *inst_cream = (vnmul_inst *)inst_base->component;
int ret;
@@ -564,15 +540,15 @@ DYNCOM_FILL_ACTION(vnmul),
int DYNCOM_TAG(vnmul)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
return instr_size;
-}
+}
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vnmul)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arch_arm_undef(cpu, bb, instr);
int m;
int n;
@@ -608,7 +584,7 @@ int DYNCOM_TRANS(vnmul)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
tmp = FPMUL(nn,mm);
tmp = FPNEG64(tmp);
mm = TRUNC32(LSHR(IBITCAST64(tmp),CONST64(32)));
- nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff)));
+ nn = TRUNC32(AND(IBITCAST64(tmp),CONST64(0xffffffff)));
LETFPS(2*d ,FPBITCAST32(nn));
LETFPS(d*2 + 1 , FPBITCAST32(mm));
}
@@ -616,7 +592,6 @@ int DYNCOM_TRANS(vnmul)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
}
#endif
-
/* ----------------------------------------------------------------------- */
/* VMUL */
/* cond 1110 0D10 Vn-- Vd-- 101X N0M0 Vm-- */
@@ -629,8 +604,6 @@ typedef struct _vmul_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vmul)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmul_inst));
vmul_inst *inst_cream = (vmul_inst *)inst_base->component;
@@ -651,8 +624,6 @@ VMUL_INST:
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
- DBG("VMUL :\n");
-
vmul_inst *inst_cream = (vmul_inst *)inst_base->component;
int ret;
@@ -678,7 +649,6 @@ DYNCOM_FILL_ACTION(vmul),
int DYNCOM_TAG(vmul)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
return instr_size;
@@ -686,8 +656,7 @@ int DYNCOM_TAG(vmul)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vmul)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
- //printf("\n\n\t\tin %s instruction is executed out.\n\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arch_arm_undef(cpu, bb, instr);
int m;
int n;
@@ -728,7 +697,7 @@ int DYNCOM_TRANS(vmul)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
hi64 = ZEXT64(hi);
lo64 = ZEXT64(lo);
v64 = OR(SHL(hi64,CONST64(32)),lo64);
- Value *n0 = FPBITCAST64(v64);
+ Value *n0 = FPBITCAST64(v64);
tmp = FPMUL(n0,m0);
Value *val64 = IBITCAST64(tmp);
hi = LSHR(val64,CONST64(32));
@@ -736,7 +705,7 @@ int DYNCOM_TRANS(vmul)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
hi = TRUNC32(hi);
lo = TRUNC32(lo);
hi = FPBITCAST32(hi);
- lo = FPBITCAST32(lo);
+ lo = FPBITCAST32(lo);
LETFPS(2*d ,lo);
LETFPS(d*2 + 1 , hi);
}
@@ -756,8 +725,6 @@ typedef struct _vadd_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vadd)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vadd_inst));
vadd_inst *inst_cream = (vadd_inst *)inst_base->component;
@@ -778,8 +745,6 @@ VADD_INST:
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
- DBG("VADD :\n");
-
vadd_inst *inst_cream = (vadd_inst *)inst_base->component;
int ret;
@@ -805,7 +770,7 @@ DYNCOM_FILL_ACTION(vadd),
int DYNCOM_TAG(vadd)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
return instr_size;
@@ -813,7 +778,7 @@ int DYNCOM_TAG(vadd)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vadd)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- DBG("\t\tin %s instruction will implement out of JIT.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction will implement out of JIT.\n", __FUNCTION__);
//arch_arm_undef(cpu, bb, instr);
int m;
int n;
@@ -849,7 +814,7 @@ int DYNCOM_TRANS(vadd)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
hi64 = ZEXT64(hi);
lo64 = ZEXT64(lo);
v64 = OR(SHL(hi64,CONST64(32)),lo64);
- Value *n0 = FPBITCAST64(v64);
+ Value *n0 = FPBITCAST64(v64);
tmp = FPADD(n0,m0);
Value *val64 = IBITCAST64(tmp);
hi = LSHR(val64,CONST64(32));
@@ -857,7 +822,7 @@ int DYNCOM_TRANS(vadd)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
hi = TRUNC32(hi);
lo = TRUNC32(lo);
hi = FPBITCAST32(hi);
- lo = FPBITCAST32(lo);
+ lo = FPBITCAST32(lo);
LETFPS(2*d ,lo);
LETFPS(d*2 + 1 , hi);
}
@@ -877,8 +842,6 @@ typedef struct _vsub_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vsub)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vsub_inst));
vsub_inst *inst_cream = (vsub_inst *)inst_base->component;
@@ -899,8 +862,6 @@ VSUB_INST:
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
- DBG("VSUB :\n");
-
vsub_inst *inst_cream = (vsub_inst *)inst_base->component;
int ret;
@@ -932,7 +893,7 @@ int DYNCOM_TAG(vsub)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vsub)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- DBG("\t\tin %s instr=0x%x, instruction is executed out of JIT.\n", __FUNCTION__, instr);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instr=0x%x, instruction is executed out of JIT.\n", __FUNCTION__, instr);
//arch_arm_undef(cpu, bb, instr);
int m;
int n;
@@ -968,7 +929,7 @@ int DYNCOM_TRANS(vsub)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
hi64 = ZEXT64(hi);
lo64 = ZEXT64(lo);
v64 = OR(SHL(hi64,CONST64(32)),lo64);
- Value *n0 = FPBITCAST64(v64);
+ Value *n0 = FPBITCAST64(v64);
tmp = FPSUB(n0,m0);
Value *val64 = IBITCAST64(tmp);
hi = LSHR(val64,CONST64(32));
@@ -976,10 +937,10 @@ int DYNCOM_TRANS(vsub)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
hi = TRUNC32(hi);
lo = TRUNC32(lo);
hi = FPBITCAST32(hi);
- lo = FPBITCAST32(lo);
+ lo = FPBITCAST32(lo);
LETFPS(2*d ,lo);
LETFPS(d*2 + 1 , hi);
- }
+ }
return No_exp;
}
#endif
@@ -996,8 +957,6 @@ typedef struct _vdiv_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vdiv)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vdiv_inst));
vdiv_inst *inst_cream = (vdiv_inst *)inst_base->component;
@@ -1018,8 +977,6 @@ VDIV_INST:
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
- DBG("VDIV :\n");
-
vdiv_inst *inst_cream = (vdiv_inst *)inst_base->component;
int ret;
@@ -1045,7 +1002,7 @@ DYNCOM_FILL_ACTION(vdiv),
int DYNCOM_TAG(vdiv)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
return instr_size;
@@ -1053,7 +1010,7 @@ int DYNCOM_TAG(vdiv)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vdiv)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arch_arm_undef(cpu, bb, instr);
int m;
int n;
@@ -1089,7 +1046,7 @@ int DYNCOM_TRANS(vdiv)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
hi64 = ZEXT64(hi);
lo64 = ZEXT64(lo);
v64 = OR(SHL(hi64,CONST64(32)),lo64);
- Value *n0 = FPBITCAST64(v64);
+ Value *n0 = FPBITCAST64(v64);
tmp = FPDIV(n0,m0);
Value *val64 = IBITCAST64(tmp);
hi = LSHR(val64,CONST64(32));
@@ -1097,10 +1054,10 @@ int DYNCOM_TRANS(vdiv)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
hi = TRUNC32(hi);
lo = TRUNC32(lo);
hi = FPBITCAST32(hi);
- lo = FPBITCAST32(lo);
+ lo = FPBITCAST32(lo);
LETFPS(2*d ,lo);
LETFPS(d*2 + 1 , hi);
- }
+ }
return No_exp;
}
#endif
@@ -1119,8 +1076,6 @@ typedef struct _vmovi_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vmovi)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovi_inst));
vmovi_inst *inst_cream = (vmovi_inst *)inst_base->component;
@@ -1163,14 +1118,14 @@ DYNCOM_FILL_ACTION(vmovi),
int DYNCOM_TAG(vmovi)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
return instr_size;
}
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vmovi)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arch_arm_undef(cpu, bb, instr);
int single = (BIT(8) == 0);
int d;
@@ -1210,8 +1165,6 @@ typedef struct _vmovr_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vmovr)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovr_inst));
vmovr_inst *inst_cream = (vmovr_inst *)inst_base->component;
@@ -1251,7 +1204,6 @@ int DYNCOM_TAG(vmovr)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t
{
int instr_size = INSTR_SIZE;
arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
- DBG("In %s, pc=0x%x, next_pc=0x%x\n", __FUNCTION__, pc, *next_pc);
if(instr >> 28 != 0xe)
*tag |= TAG_CONDITIONAL;
@@ -1260,7 +1212,6 @@ int DYNCOM_TAG(vmovr)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vmovr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- DBG("\t\tin %s VMOV \n", __FUNCTION__);
int single = BIT(8) == 0;
int d = (single ? BITS(12,15)<<1 | BIT(22) : BIT(22) << 4 | BITS(12,15));
int m = (single ? BITS(0, 3)<<1 | BIT(5) : BITS(0, 3) | BIT(5)<<4);
@@ -1311,8 +1262,6 @@ VABS_INST:
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
- DBG("VABS :\n");
-
vabs_inst *inst_cream = (vabs_inst *)inst_base->component;
int ret;
@@ -1338,7 +1287,6 @@ DYNCOM_FILL_ACTION(vabs),
int DYNCOM_TAG(vabs)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
return instr_size;
@@ -1346,7 +1294,6 @@ int DYNCOM_TAG(vabs)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vabs)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arch_arm_undef(cpu, bb, instr);
int single = BIT(8) == 0;
int d = (single ? BITS(12,15)<<1 | BIT(22) : BIT(22) << 4 | BITS(12,15));
@@ -1376,7 +1323,7 @@ int DYNCOM_TRANS(vabs)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
hi = TRUNC32(hi);
lo = TRUNC32(lo);
hi = FPBITCAST32(hi);
- lo = FPBITCAST32(lo);
+ lo = FPBITCAST32(lo);
LETFPS(2*d ,lo);
LETFPS(d*2 + 1 , hi);
}
@@ -1417,8 +1364,6 @@ VNEG_INST:
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
- DBG("VNEG :\n");
-
vneg_inst *inst_cream = (vneg_inst *)inst_base->component;
int ret;
@@ -1444,7 +1389,7 @@ DYNCOM_FILL_ACTION(vneg),
int DYNCOM_TAG(vneg)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
return instr_size;
@@ -1452,7 +1397,7 @@ int DYNCOM_TAG(vneg)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vneg)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arch_arm_undef(cpu, bb, instr);
int single = BIT(8) == 0;
int d = (single ? BITS(12,15)<<1 | BIT(22) : BIT(22) << 4 | BITS(12,15));
@@ -1482,7 +1427,7 @@ int DYNCOM_TRANS(vneg)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
hi = TRUNC32(hi);
lo = TRUNC32(lo);
hi = FPBITCAST32(hi);
- lo = FPBITCAST32(lo);
+ lo = FPBITCAST32(lo);
LETFPS(2*d ,lo);
LETFPS(d*2 + 1 , hi);
}
@@ -1502,8 +1447,6 @@ typedef struct _vsqrt_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vsqrt)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vsqrt_inst));
vsqrt_inst *inst_cream = (vsqrt_inst *)inst_base->component;
@@ -1524,8 +1467,6 @@ VSQRT_INST:
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
- DBG("VSQRT :\n");
-
vsqrt_inst *inst_cream = (vsqrt_inst *)inst_base->component;
int ret;
@@ -1551,7 +1492,7 @@ DYNCOM_FILL_ACTION(vsqrt),
int DYNCOM_TAG(vsqrt)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
return instr_size;
@@ -1559,7 +1500,7 @@ int DYNCOM_TAG(vsqrt)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vsqrt)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arch_arm_undef(cpu, bb, instr);
int dp_op = (BIT(8) == 1);
int d = dp_op ? BITS(12,15) | BIT(22) << 4 : BIT(22) | BITS(12,15) << 1;
@@ -1572,7 +1513,7 @@ int DYNCOM_TRANS(vsqrt)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
v = OR(v,tmp);
v = FPSQRT(FPBITCAST64(v));
tmp = TRUNC32(LSHR(IBITCAST64(v),CONST64(32)));
- v = TRUNC32(AND(IBITCAST64(v),CONST64( 0xffffffff)));
+ v = TRUNC32(AND(IBITCAST64(v),CONST64( 0xffffffff)));
LETFPS(2 * d , FPBITCAST32(v));
LETFPS(2 * d + 1, FPBITCAST32(tmp));
}else {
@@ -1597,8 +1538,6 @@ typedef struct _vcmp_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vcmp)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vcmp_inst));
vcmp_inst *inst_cream = (vcmp_inst *)inst_base->component;
@@ -1619,8 +1558,6 @@ VCMP_INST:
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
- DBG("VCMP(1) :\n");
-
vcmp_inst *inst_cream = (vcmp_inst *)inst_base->component;
int ret;
@@ -1653,7 +1590,7 @@ int DYNCOM_TAG(vcmp)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vcmp)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- DBG("\t\tin %s instruction is executed out of JIT.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction is executed out of JIT.\n", __FUNCTION__);
//arch_arm_undef(cpu, bb, instr);
int dp_op = (BIT(8) == 1);
int d = dp_op ? BITS(12,15) | BIT(22) << 4 : BIT(22) | BITS(12,15) << 1;
@@ -1675,7 +1612,7 @@ int DYNCOM_TRANS(vcmp)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
v = OR(v,tmp);
z = FPCMP_OEQ(FPBITCAST64(v),FPBITCAST64(v1));
n = FPCMP_OLT(FPBITCAST64(v),FPBITCAST64(v1));
- c = FPCMP_OGE(FPBITCAST64(v),FPBITCAST64(v1));
+ c = FPCMP_OGE(FPBITCAST64(v),FPBITCAST64(v1));
tmp = FPCMP_UNO(FPBITCAST64(v),FPBITCAST64(v1));
v1 = tmp;
c = OR(c,tmp);
@@ -1683,14 +1620,14 @@ int DYNCOM_TRANS(vcmp)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
z = SHL(ZEXT32(z),CONST32(30));
c = SHL(ZEXT32(c),CONST32(29));
v1 = SHL(ZEXT32(v1),CONST(28));
- nzcv = OR(OR(OR(n,z),c),v1);
+ nzcv = OR(OR(OR(n,z),c),v1);
v = R(VFP_FPSCR);
tmp = OR(nzcv,AND(v,CONST32(0x0fffffff)));
LET(VFP_FPSCR,tmp);
}else {
z = FPCMP_OEQ(FR32(d),FR32(m));
n = FPCMP_OLT(FR32(d),FR32(m));
- c = FPCMP_OGE(FR32(d),FR32(m));
+ c = FPCMP_OGE(FR32(d),FR32(m));
tmp = FPCMP_UNO(FR32(d),FR32(m));
c = OR(c,tmp);
v1 = tmp;
@@ -1698,7 +1635,7 @@ int DYNCOM_TRANS(vcmp)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
z = SHL(ZEXT32(z),CONST32(30));
c = SHL(ZEXT32(c),CONST32(29));
v1 = SHL(ZEXT32(v1),CONST(28));
- nzcv = OR(OR(OR(n,z),c),v1);
+ nzcv = OR(OR(OR(n,z),c),v1);
v = R(VFP_FPSCR);
tmp = OR(nzcv,AND(v,CONST32(0x0fffffff)));
LET(VFP_FPSCR,tmp);
@@ -1719,8 +1656,6 @@ typedef struct _vcmp2_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vcmp2)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vcmp2_inst));
vcmp2_inst *inst_cream = (vcmp2_inst *)inst_base->component;
@@ -1741,8 +1676,6 @@ VCMP2_INST:
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
- DBG("VCMP(2) :\n");
-
vcmp2_inst *inst_cream = (vcmp2_inst *)inst_base->component;
int ret;
@@ -1775,7 +1708,7 @@ int DYNCOM_TAG(vcmp2)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vcmp2)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- DBG("\t\tin %s instruction will executed out of JIT.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction will executed out of JIT.\n", __FUNCTION__);
//arch_arm_undef(cpu, bb, instr);
int dp_op = (BIT(8) == 1);
int d = dp_op ? BITS(12,15) | BIT(22) << 4 : BIT(22) | BITS(12,15) << 1;
@@ -1795,7 +1728,7 @@ int DYNCOM_TRANS(vcmp2)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
v = OR(v,tmp);
z = FPCMP_OEQ(FPBITCAST64(v),FPBITCAST64(v1));
n = FPCMP_OLT(FPBITCAST64(v),FPBITCAST64(v1));
- c = FPCMP_OGE(FPBITCAST64(v),FPBITCAST64(v1));
+ c = FPCMP_OGE(FPBITCAST64(v),FPBITCAST64(v1));
tmp = FPCMP_UNO(FPBITCAST64(v),FPBITCAST64(v1));
v1 = tmp;
c = OR(c,tmp);
@@ -1803,7 +1736,7 @@ int DYNCOM_TRANS(vcmp2)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
z = SHL(ZEXT32(z),CONST32(30));
c = SHL(ZEXT32(c),CONST32(29));
v1 = SHL(ZEXT32(v1),CONST(28));
- nzcv = OR(OR(OR(n,z),c),v1);
+ nzcv = OR(OR(OR(n,z),c),v1);
v = R(VFP_FPSCR);
tmp = OR(nzcv,AND(v,CONST32(0x0fffffff)));
LET(VFP_FPSCR,tmp);
@@ -1812,7 +1745,7 @@ int DYNCOM_TRANS(vcmp2)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
v1 = FPBITCAST32(v1);
z = FPCMP_OEQ(FR32(d),v1);
n = FPCMP_OLT(FR32(d),v1);
- c = FPCMP_OGE(FR32(d),v1);
+ c = FPCMP_OGE(FR32(d),v1);
tmp = FPCMP_UNO(FR32(d),v1);
c = OR(c,tmp);
v1 = tmp;
@@ -1820,7 +1753,7 @@ int DYNCOM_TRANS(vcmp2)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
z = SHL(ZEXT32(z),CONST32(30));
c = SHL(ZEXT32(c),CONST32(29));
v1 = SHL(ZEXT32(v1),CONST(28));
- nzcv = OR(OR(OR(n,z),c),v1);
+ nzcv = OR(OR(OR(n,z),c),v1);
v = R(VFP_FPSCR);
tmp = OR(nzcv,AND(v,CONST32(0x0fffffff)));
LET(VFP_FPSCR,tmp);
@@ -1841,8 +1774,6 @@ typedef struct _vcvtbds_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbds)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vcvtbds_inst));
vcvtbds_inst *inst_cream = (vcvtbds_inst *)inst_base->component;
@@ -1863,8 +1794,6 @@ VCVTBDS_INST:
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
- DBG("VCVT(BDS) :\n");
-
vcvtbds_inst *inst_cream = (vcvtbds_inst *)inst_base->component;
int ret;
@@ -1897,7 +1826,7 @@ int DYNCOM_TAG(vcvtbds)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vcvtbds)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- DBG("\t\tin %s instruction is executed out.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction is executed out.\n", __FUNCTION__);
//arch_arm_undef(cpu, bb, instr);
int dp_op = (BIT(8) == 1);
int d = dp_op ? BITS(12,15) << 1 | BIT(22) : BIT(22) << 4 | BITS(12,15);
@@ -1911,7 +1840,7 @@ int DYNCOM_TRANS(vcvtbds)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc)
tmp = ZEXT64(IBITCAST32(FR32(2 * m)));
v1 = OR(v,tmp);
tmp = FPTRUNC(32,FPBITCAST64(v1));
- LETFPS(d,tmp);
+ LETFPS(d,tmp);
}else {
v = FR32(m);
tmp = FPEXT(64,v);
@@ -1937,7 +1866,7 @@ typedef struct _vcvtbff_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbff)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;VFP_DEBUG_UNTESTED(VCVTBFF);
+ VFP_DEBUG_UNTESTED(VCVTBFF);
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vcvtbff_inst));
vcvtbff_inst *inst_cream = (vcvtbff_inst *)inst_base->component;
@@ -1959,8 +1888,6 @@ VCVTBFF_INST:
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
- DBG("VCVT(BFF) :\n");
-
vcvtbff_inst *inst_cream = (vcvtbff_inst *)inst_base->component;
int ret;
@@ -1986,14 +1913,14 @@ DYNCOM_FILL_ACTION(vcvtbff),
int DYNCOM_TAG(vcvtbff)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
return instr_size;
}
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vcvtbff)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
arch_arm_undef(cpu, bb, instr);
return No_exp;
}
@@ -2011,8 +1938,6 @@ typedef struct _vcvtbfi_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbfi)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vcvtbfi_inst));
vcvtbfi_inst *inst_cream = (vcvtbfi_inst *)inst_base->component;
@@ -2024,7 +1949,6 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vcvtbfi)(unsigned int inst, int index)
inst_cream->dp_operation = BIT(inst, 8);
inst_cream->instr = inst;
-
return inst_base;
}
#endif
@@ -2034,8 +1958,6 @@ VCVTBFI_INST:
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
- DBG("VCVT(BFI) :\n");
-
vcvtbfi_inst *inst_cream = (vcvtbfi_inst *)inst_base->component;
int ret;
@@ -2061,8 +1983,7 @@ DYNCOM_FILL_ACTION(vcvtbfi),
int DYNCOM_TAG(vcvtbfi)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
- DBG("\t\tin %s, instruction will be executed out of JIT.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s, instruction will be executed out of JIT.\n", __FUNCTION__);
//arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
return instr_size;
@@ -2070,17 +1991,17 @@ int DYNCOM_TAG(vcvtbfi)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vcvtbfi)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- DBG("\t\tin %s, instruction will be executed out of JIT.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s, instruction will be executed out of JIT.\n", __FUNCTION__);
//arch_arm_undef(cpu, bb, instr);
unsigned int opc2 = BITS(16,18);
- int to_integer = ((opc2 >> 2) == 1);
+ int to_integer = ((opc2 >> 2) == 1);
int dp_op = (BIT(8) == 1);
unsigned int op = BIT(7);
int m,d;
Value* v;
Value* hi;
Value* lo;
- Value* v64;
+ Value* v64;
if(to_integer){
d = BIT(22) | (BITS(12,15) << 1);
if(dp_op)
@@ -2092,15 +2013,15 @@ int DYNCOM_TRANS(vcvtbfi)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc)
if(dp_op)
d = BITS(12,15) | BIT(22) << 4;
else
- d = BIT(22) | BITS(12,15) << 1;
+ d = BIT(22) | BITS(12,15) << 1;
}
if(to_integer){
if(dp_op){
lo = FR32(m * 2);
- hi = FR32(m * 2 + 1);
+ hi = FR32(m * 2 + 1);
hi = ZEXT64(IBITCAST32(hi));
lo = ZEXT64(IBITCAST32(lo));
- v64 = OR(SHL(hi,CONST64(32)),lo);
+ v64 = OR(SHL(hi,CONST64(32)),lo);
if(BIT(16)){
v = FPTOSI(32,FPBITCAST64(v64));
}
@@ -2112,7 +2033,6 @@ int DYNCOM_TRANS(vcvtbfi)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc)
}else {
v = FR32(m);
if(BIT(16)){
-
v = FPTOSI(32,v);
}
else
@@ -2120,10 +2040,10 @@ int DYNCOM_TRANS(vcvtbfi)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc)
LETFPS(d,FPBITCAST32(v));
}
}else {
- if(dp_op){
+ if(dp_op){
v = IBITCAST32(FR32(m));
if(BIT(7))
- v64 = SITOFP(64,v);
+ v64 = SITOFP(64,v);
else
v64 = UITOFP(64,v);
v = IBITCAST64(v64);
@@ -2149,7 +2069,7 @@ int DYNCOM_TRANS(vcvtbfi)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc)
* @param cpu
* @param instr
*
-* @return
+* @return
*/
int vcvtbfi_instr_impl(arm_core_t* cpu, uint32 instr){
int dp_operation = BIT(8);
@@ -2183,8 +2103,6 @@ typedef struct _vmovbrs_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrs)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbrs_inst));
vmovbrs_inst *inst_cream = (vmovbrs_inst *)inst_base->component;
@@ -2224,26 +2142,22 @@ DYNCOM_FILL_ACTION(vmovbrs),
int DYNCOM_TAG(vmovbrs)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
return instr_size;
}
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vmovbrs)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- DBG("VMOV(BRS) :\n");
int to_arm = BIT(20) == 1;
int t = BITS(12, 15);
int n = BIT(7) | BITS(16, 19)<<1;
if (to_arm)
{
- DBG("\tr%d <= s%d\n", t, n);
LET(t, IBITCAST32(FR32(n)));
}
else
{
- DBG("\ts%d <= r%d\n", n, t);
LETFPS(n, FPBITCAST32(R(t)));
}
return No_exp;
@@ -2263,8 +2177,6 @@ typedef struct _vmsr_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vmsr)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmsr_inst));
vmsr_inst *inst_cream = (vmsr_inst *)inst_base->component;
@@ -2306,7 +2218,6 @@ DYNCOM_FILL_ACTION(vmsr),
int DYNCOM_TAG(vmsr)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
return instr_size;
@@ -2314,11 +2225,9 @@ int DYNCOM_TAG(vmsr)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vmsr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arch_arm_undef(cpu, bb, instr);
- DBG("VMSR :");
if(RD == 15) {
- printf("in %s is not implementation.\n", __FUNCTION__);
+ LOG_ERROR(Core_ARM11, "in %s is not implementation.\n", __FUNCTION__);
exit(-1);
}
@@ -2328,7 +2237,6 @@ int DYNCOM_TRANS(vmsr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
if (reg == 1)
{
LET(VFP_FPSCR, R(Rt));
- DBG("\tflags <= fpscr\n");
}
else
{
@@ -2336,10 +2244,8 @@ int DYNCOM_TRANS(vmsr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
{
case 8:
LET(VFP_FPEXC, R(Rt));
- DBG("\tfpexc <= r%d \n", Rt);
break;
default:
- DBG("\tSUBARCHITECTURE DEFINED\n");
break;
}
}
@@ -2362,8 +2268,6 @@ typedef struct _vmovbrc_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrc)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbrc_inst));
vmovbrc_inst *inst_cream = (vmovbrc_inst *)inst_base->component;
@@ -2405,14 +2309,14 @@ DYNCOM_FILL_ACTION(vmovbrc),
int DYNCOM_TAG(vmovbrc)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
return instr_size;
}
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vmovbrc)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
arch_arm_undef(cpu, bb, instr);
return No_exp;
}
@@ -2431,8 +2335,6 @@ typedef struct _vmrs_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vmrs)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmrs_inst));
vmrs_inst *inst_cream = (vmrs_inst *)inst_base->component;
@@ -2458,46 +2360,39 @@ VMRS_INST:
vmrs_inst *inst_cream = (vmrs_inst *)inst_base->component;
- DBG("VMRS :");
-
if (inst_cream->reg == 1) /* FPSCR */
{
if (inst_cream->Rt != 15)
- {
+ {
cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_OFFSET(VFP_FPSCR)];
- DBG("\tr%d <= fpscr[%08x]\n", inst_cream->Rt, cpu->VFP[VFP_OFFSET(VFP_FPSCR)]);
}
else
- {
+ {
cpu->NFlag = (cpu->VFP[VFP_OFFSET(VFP_FPSCR)] >> 31) & 1;
cpu->ZFlag = (cpu->VFP[VFP_OFFSET(VFP_FPSCR)] >> 30) & 1;
cpu->CFlag = (cpu->VFP[VFP_OFFSET(VFP_FPSCR)] >> 29) & 1;
cpu->VFlag = (cpu->VFP[VFP_OFFSET(VFP_FPSCR)] >> 28) & 1;
- DBG("\tflags <= fpscr[%1xxxxxxxx]\n", cpu->VFP[VFP_OFFSET(VFP_FPSCR)]>>28);
}
- }
+ }
else
{
switch (inst_cream->reg)
{
case 0:
cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_OFFSET(VFP_FPSID)];
- DBG("\tr%d <= fpsid[%08x]\n", inst_cream->Rt, cpu->VFP[VFP_OFFSET(VFP_FPSID)]);
break;
case 6:
/* MVFR1, VFPv3 only ? */
- DBG("\tr%d <= MVFR1 unimplemented\n", inst_cream->Rt);
+ LOG_TRACE(Core_ARM11, "\tr%d <= MVFR1 unimplemented\n", inst_cream->Rt);
break;
case 7:
/* MVFR0, VFPv3 only? */
- DBG("\tr%d <= MVFR0 unimplemented\n", inst_cream->Rt);
+ LOG_TRACE(Core_ARM11, "\tr%d <= MVFR0 unimplemented\n", inst_cream->Rt);
break;
case 8:
cpu->Reg[inst_cream->Rt] = cpu->VFP[VFP_OFFSET(VFP_FPEXC)];
- DBG("\tr%d <= fpexc[%08x]\n", inst_cream->Rt, cpu->VFP[VFP_OFFSET(VFP_FPEXC)]);
break;
default:
- DBG("\tSUBARCHITECTURE DEFINED\n");
break;
}
}
@@ -2516,8 +2411,6 @@ DYNCOM_FILL_ACTION(vmrs),
int DYNCOM_TAG(vmrs)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
- DBG("\t\tin %s .\n", __FUNCTION__);
//arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
return instr_size;
@@ -2525,25 +2418,21 @@ int DYNCOM_TAG(vmrs)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vmrs)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arch_arm_undef(cpu, bb, instr);
Value *data = NULL;
int reg = BITS(16, 19);;
int Rt = BITS(12, 15);
- DBG("VMRS : reg=%d, Rt=%d\n", reg, Rt);
if (reg == 1)
{
if (Rt != 15)
{
LET(Rt, R(VFP_FPSCR));
- DBG("\tr%d <= fpscr\n", Rt);
}
else
{
//LET(Rt, R(VFP_FPSCR));
update_cond_from_fpscr(cpu, instr, bb, pc);
- DBG("In %s, \tflags <= fpscr\n", __FUNCTION__);
}
}
else
@@ -2552,22 +2441,19 @@ int DYNCOM_TRANS(vmrs)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
{
case 0:
LET(Rt, R(VFP_FPSID));
- DBG("\tr%d <= fpsid\n", Rt);
break;
case 6:
/* MVFR1, VFPv3 only ? */
- DBG("\tr%d <= MVFR1 unimplemented\n", Rt);
+ LOG_TRACE(Core_ARM11, "\tr%d <= MVFR1 unimplemented\n", Rt);
break;
case 7:
/* MVFR0, VFPv3 only? */
- DBG("\tr%d <= MVFR0 unimplemented\n", Rt);
+ LOG_TRACE(Core_ARM11, "\tr%d <= MVFR0 unimplemented\n", Rt);
break;
case 8:
LET(Rt, R(VFP_FPEXC));
- DBG("\tr%d <= fpexc\n", Rt);
break;
default:
- DBG("\tSUBARCHITECTURE DEFINED\n");
break;
}
}
@@ -2591,8 +2477,6 @@ typedef struct _vmovbcr_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbcr)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbcr_inst));
vmovbcr_inst *inst_cream = (vmovbcr_inst *)inst_base->component;
@@ -2634,14 +2518,14 @@ DYNCOM_FILL_ACTION(vmovbcr),
int DYNCOM_TAG(vmovbcr)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
return instr_size;
}
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vmovbcr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
+ LOG_TRACE(Core_ARM11, "\t\tin %s instruction is not implemented.\n", __FUNCTION__);
arch_arm_undef(cpu, bb, instr);
return No_exp;
}
@@ -2667,8 +2551,6 @@ typedef struct _vmovbrrss_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrrss)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbrrss_inst));
vmovbrrss_inst *inst_cream = (vmovbrrss_inst *)inst_base->component;
@@ -2751,8 +2633,6 @@ typedef struct _vmovbrrd_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrrd)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vmovbrrd_inst));
vmovbrrd_inst *inst_cream = (vmovbrrd_inst *)inst_base->component;
@@ -2777,7 +2657,7 @@ VMOVBRRD_INST:
vmovbrrd_inst *inst_cream = (vmovbrrd_inst *)inst_base->component;
- VMOVBRRD(cpu, inst_cream->to_arm, inst_cream->t, inst_cream->t2, inst_cream->m,
+ VMOVBRRD(cpu, inst_cream->to_arm, inst_cream->t, inst_cream->t2, inst_cream->m,
&(cpu->Reg[inst_cream->t]), &(cpu->Reg[inst_cream->t2]));
}
cpu->Reg[15] += GET_INST_SIZE(cpu);
@@ -2794,7 +2674,6 @@ DYNCOM_FILL_ACTION(vmovbrrd),
int DYNCOM_TAG(vmovbrrd)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
if(instr >> 28 != 0xe)
*tag |= TAG_CONDITIONAL;
@@ -2803,7 +2682,6 @@ int DYNCOM_TAG(vmovbrrd)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vmovbrrd)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arch_arm_undef(cpu, bb, instr);
int to_arm = BIT(20) == 1;
int t = BITS(12, 15);
@@ -2841,8 +2719,6 @@ typedef struct _vstr_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vstr)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vstr_inst));
vstr_inst *inst_cream = (vstr_inst *)inst_base->component;
@@ -2896,7 +2772,6 @@ int DYNCOM_TAG(vstr)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
{
int instr_size = INSTR_SIZE;
arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
- DBG("In %s, pc=0x%x, next_pc=0x%x\n", __FUNCTION__, pc, *next_pc);
*tag |= TAG_NEW_BB;
if(instr >> 28 != 0xe)
*tag |= TAG_CONDITIONAL;
@@ -2914,7 +2789,6 @@ int DYNCOM_TRANS(vstr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
Value* base = (n == 15) ? ADD(AND(R(n), CONST(0xFFFFFFFC)), CONST(8)): R(n);
Value* Addr = add ? ADD(base, CONST(imm32)) : SUB(base, CONST(imm32));
- DBG("VSTR :\n");
//if(single)
// bb = arch_check_mm(cpu, bb, Addr, 4, 0, cpu->dyncom_engine->bb_trap);
//else
@@ -2951,8 +2825,6 @@ typedef struct _vpush_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vpush)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vpush_inst));
vpush_inst *inst_cream = (vpush_inst *)inst_base->component;
@@ -3010,7 +2882,6 @@ int DYNCOM_TAG(vpush)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t
{
int instr_size = INSTR_SIZE;
arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
- DBG("In %s, pc=0x%x, next_pc=0x%x\n", __FUNCTION__, pc, *next_pc);
*tag |= TAG_NEW_BB;
if(instr >> 28 != 0xe)
*tag |= TAG_CONDITIONAL;
@@ -3025,7 +2896,6 @@ int DYNCOM_TRANS(vpush)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
int imm32 = BITS(0, 7)<<2;
int regs = (single ? BITS(0, 7) : BITS(1, 7));
- DBG("\t\tin %s \n", __FUNCTION__);
Value* Addr = SUB(R(13), CONST(imm32));
//if(single)
// bb = arch_check_mm(cpu, bb, Addr, regs * 4, 0, cpu->dyncom_engine->bb_trap);
@@ -3079,8 +2949,6 @@ typedef struct _vstm_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vstm)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vstm_inst));
vstm_inst *inst_cream = (vstm_inst *)inst_base->component;
@@ -3127,10 +2995,9 @@ VSTM_INST: /* encoding 1 */
}
}
if (inst_cream->wback){
- cpu->Reg[inst_cream->n] = (inst_cream->add ? cpu->Reg[inst_cream->n] + inst_cream->imm32 :
+ cpu->Reg[inst_cream->n] = (inst_cream->add ? cpu->Reg[inst_cream->n] + inst_cream->imm32 :
cpu->Reg[inst_cream->n] - inst_cream->imm32);
}
-
}
cpu->Reg[15] += 4;
INC_PC(sizeof(vstm_inst));
@@ -3147,10 +3014,8 @@ DYNCOM_FILL_ACTION(vstm),
int DYNCOM_TAG(vstm)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
- DBG("In %s, pc=0x%x, next_pc=0x%x\n", __FUNCTION__, pc, *next_pc);
*tag |= TAG_NEW_BB;
if(instr >> 28 != 0xe)
*tag |= TAG_CONDITIONAL;
@@ -3170,30 +3035,26 @@ int DYNCOM_TRANS(vstm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
int regs = single ? BITS(0, 7) : BITS(1, 7);
Value* Addr = SELECT(CONST1(add), R(n), SUB(R(n), CONST(imm32)));
- DBG("VSTM \n");
//if(single)
// bb = arch_check_mm(cpu, bb, Addr, regs * 4, 0, cpu->dyncom_engine->bb_trap);
//else
// bb = arch_check_mm(cpu, bb, Addr, regs * 8, 0, cpu->dyncom_engine->bb_trap);
- int i;
+ int i;
Value* phys_addr;
for (i = 0; i < regs; i++)
{
if (single)
{
-
//Memory::Write32(addr, cpu->ExtReg[inst_cream->d+i]);
/* if R(i) is R15? */
//memory_write(cpu, bb, Addr, RSPR(d + i), 32);
memory_write(cpu, bb, Addr, IBITCAST32(FR32(d + i)),32);
bb = cpu->dyncom_engine->bb;
- //DBG("\taddr[%x] <= s%d=[%x]\n", addr, inst_cream->d+i, cpu->ExtReg[inst_cream->d+i]);
Addr = ADD(Addr, CONST(4));
}
else
{
-
//Memory::Write32(addr, cpu->ExtReg[(inst_cream->d+i)*2]);
//memory_write(cpu, bb, Addr, RSPR((d + i) * 2), 32);
memory_write(cpu, bb, Addr, IBITCAST32(FR32((d + i) * 2)),32);
@@ -3203,16 +3064,14 @@ int DYNCOM_TRANS(vstm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
//memory_write(cpu, bb, ADD(Addr, CONST(4)), RSPR((d + i) * 2 + 1), 32);
memory_write(cpu, bb, ADD(Addr, CONST(4)), IBITCAST32(FR32((d + i) * 2 + 1)), 32);
bb = cpu->dyncom_engine->bb;
- //DBG("\taddr[%x-%x] <= s[%d-%d]=[%x-%x]\n", addr+4, addr, (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, cpu->ExtReg[(inst_cream->d+i)*2+1], cpu->ExtReg[(inst_cream->d+i)*2]);
//addr += 8;
Addr = ADD(Addr, CONST(8));
}
}
if (wback){
- //cpu->Reg[n] = (add ? cpu->Reg[n] + imm32 :
+ //cpu->Reg[n] = (add ? cpu->Reg[n] + imm32 :
// cpu->Reg[n] - imm32);
LET(n, SELECT(CONST1(add), ADD(R(n), CONST(imm32)), SUB(R(n), CONST(imm32))));
- DBG("\twback r%d, add=%d, imm32=%d\n", n, add, imm32);
}
return No_exp;
}
@@ -3232,8 +3091,6 @@ typedef struct _vpop_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vpop)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vpop_inst));
vpop_inst *inst_cream = (vpop_inst *)inst_base->component;
@@ -3296,11 +3153,9 @@ DYNCOM_FILL_ACTION(vpop),
int DYNCOM_TAG(vpop)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
/* Should check if PC is destination register */
arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
- DBG("In %s, pc=0x%x, next_pc=0x%x\n", __FUNCTION__, pc, *next_pc);
*tag |= TAG_NEW_BB;
if(instr >> 28 != 0xe)
*tag |= TAG_CONDITIONAL;
@@ -3310,7 +3165,6 @@ int DYNCOM_TAG(vpop)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *
#endif
#ifdef VFP_DYNCOM_TRANS
int DYNCOM_TRANS(vpop)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- DBG("\t\tin %s instruction .\n", __FUNCTION__);
//arch_arm_undef(cpu, bb, instr);
int single = BIT(8) == 0;
int d = (single ? BITS(12, 15)<<1|BIT(22) : BITS(12, 15)|(BIT(22)<<4));
@@ -3320,15 +3174,13 @@ int DYNCOM_TRANS(vpop)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
int i;
unsigned int value1, value2;
- DBG("VPOP :\n");
-
Value* Addr = R(13);
Value* val;
//if(single)
// bb = arch_check_mm(cpu, bb, Addr, regs * 4, 1, cpu->dyncom_engine->bb_trap);
//else
// bb = arch_check_mm(cpu, bb, Addr, regs * 4, 1, cpu->dyncom_engine->bb_trap);
- //Value* phys_addr;
+ //Value* phys_addr;
for (i = 0; i < regs; i++)
{
if (single)
@@ -3374,8 +3226,6 @@ typedef struct _vldr_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vldr)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vldr_inst));
vldr_inst *inst_cream = (vldr_inst *)inst_base->component;
@@ -3432,11 +3282,9 @@ DYNCOM_FILL_ACTION(vldr),
int DYNCOM_TAG(vldr)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
/* Should check if PC is destination register */
arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
- DBG("In %s, pc=0x%x, next_pc=0x%x\n", __FUNCTION__, pc, *next_pc);
*tag |= TAG_NEW_BB;
if(instr >> 28 != 0xe)
*tag |= TAG_CONDITIONAL;
@@ -3454,7 +3302,6 @@ int DYNCOM_TRANS(vldr)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
int imm32 = BITS(0, 7)<<2;
int regs = (single ? BITS(0, 7) : BITS(1, 7));
Value* base = R(n);
- DBG("\t\tin %s .\n", __FUNCTION__);
if(n == 15){
base = ADD(AND(base, CONST(0xFFFFFFFC)), CONST(8));
}
@@ -3506,8 +3353,6 @@ typedef struct _vldm_inst {
#ifdef VFP_INTERPRETER_TRANS
ARM_INST_PTR INTERPRETER_TRANSLATE(vldm)(unsigned int inst, int index)
{
- VFP_DEBUG_TRANSLATE;
-
arm_inst *inst_base = (arm_inst *)AllocBuffer(sizeof(arm_inst) + sizeof(vldm_inst));
vldm_inst *inst_cream = (vldm_inst *)inst_base->component;
@@ -3554,11 +3399,9 @@ VLDM_INST:
}
}
if (inst_cream->wback){
- cpu->Reg[inst_cream->n] = (inst_cream->add ? cpu->Reg[inst_cream->n] + inst_cream->imm32 :
+ cpu->Reg[inst_cream->n] = (inst_cream->add ? cpu->Reg[inst_cream->n] + inst_cream->imm32 :
cpu->Reg[inst_cream->n] - inst_cream->imm32);
- DBG("\twback r%d[%x]\n", inst_cream->n, cpu->Reg[inst_cream->n]);
}
-
}
cpu->Reg[15] += GET_INST_SIZE(cpu);
INC_PC(sizeof(vldm_inst));
@@ -3574,10 +3417,8 @@ DYNCOM_FILL_ACTION(vldm),
int DYNCOM_TAG(vldm)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- //DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
//arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
- DBG("In %s, pc=0x%x, next_pc=0x%x\n", __FUNCTION__, pc, *next_pc);
*tag |= TAG_NEW_BB;
if(instr >> 28 != 0xe)
*tag |= TAG_CONDITIONAL;
@@ -3601,15 +3442,13 @@ int DYNCOM_TRANS(vldm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
//else
// bb = arch_check_mm(cpu, bb, Addr, regs * 4, 1, cpu->dyncom_engine->bb_trap);
- DBG("VLDM \n");
- int i;
+ int i;
//Value* phys_addr;
Value* val;
for (i = 0; i < regs; i++)
{
if (single)
{
-
//Memory::Write32(addr, cpu->ExtReg[inst_cream->d+i]);
/* if R(i) is R15? */
memory_read(cpu, bb, Addr, 0, 32);
@@ -3617,7 +3456,6 @@ int DYNCOM_TRANS(vldm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
val = new LoadInst(cpu->dyncom_engine->read_value, "", false, bb);
//LETS(d + i, val);
LETFPS(d + i, FPBITCAST32(val));
- //DBG("\taddr[%x] <= s%d=[%x]\n", addr, inst_cream->d+i, cpu->ExtReg[inst_cream->d+i]);
Addr = ADD(Addr, CONST(4));
}
else
@@ -3632,16 +3470,14 @@ int DYNCOM_TRANS(vldm)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
LETFPS((d + i) * 2 + 1, FPBITCAST32(val));
//Memory::Write(addr + 4, phys_addr, cpu->ExtReg[(inst_cream->d+i)*2 + 1], 32);
- //DBG("\taddr[%x-%x] <= s[%d-%d]=[%x-%x]\n", addr+4, addr, (inst_cream->d+i)*2+1, (inst_cream->d+i)*2, cpu->ExtReg[(inst_cream->d+i)*2+1], cpu->ExtReg[(inst_cream->d+i)*2]);
//addr += 8;
Addr = ADD(Addr, CONST(8));
}
}
if (wback){
- //cpu->Reg[n] = (add ? cpu->Reg[n] + imm32 :
+ //cpu->Reg[n] = (add ? cpu->Reg[n] + imm32 :
// cpu->Reg[n] - imm32);
LET(n, SELECT(CONST1(add), ADD(R(n), CONST(imm32)), SUB(R(n), CONST(imm32))));
- DBG("\twback r%d, add=%d, imm32=%d\n", n, add, imm32);
}
return No_exp;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-23 01:54:47 +0100