summaryrefslogtreecommitdiffstats
path: root/src/core
diff options
context:
space:
mode:
authorbunnei <ericbunnie@gmail.com>2014-04-26 07:48:24 +0200
committerbunnei <ericbunnie@gmail.com>2014-04-26 07:48:24 +0200
commit9e047e32d4973cb01f96116027e80639aa9f4280 (patch)
treeedc15feae0f43943ddda63b41ca01e3074630618 /src/core
parentadded preliminary DataSynchronizationBarrier support with simple DMA copy (diff)
downloadyuzu-9e047e32d4973cb01f96116027e80639aa9f4280.tar
yuzu-9e047e32d4973cb01f96116027e80639aa9f4280.tar.gz
yuzu-9e047e32d4973cb01f96116027e80639aa9f4280.tar.bz2
yuzu-9e047e32d4973cb01f96116027e80639aa9f4280.tar.lz
yuzu-9e047e32d4973cb01f96116027e80639aa9f4280.tar.xz
yuzu-9e047e32d4973cb01f96116027e80639aa9f4280.tar.zst
yuzu-9e047e32d4973cb01f96116027e80639aa9f4280.zip
Diffstat (limited to 'src/core')
-rw-r--r--src/core/hle/service/gsp.cpp38
1 files changed, 37 insertions, 1 deletions
diff --git a/src/core/hle/service/gsp.cpp b/src/core/hle/service/gsp.cpp
index df23ac542..24e9f18dc 100644
--- a/src/core/hle/service/gsp.cpp
+++ b/src/core/hle/service/gsp.cpp
@@ -5,14 +5,50 @@
#include "common/log.h"
+#include "core/mem_map.h"
#include "core/hle/hle.h"
#include "core/hle/service/gsp.h"
+#include "core/hw/lcd.h"
+
////////////////////////////////////////////////////////////////////////////////////////////////////
// Namespace GSP_GPU
namespace GSP_GPU {
+enum {
+ REG_FRAMEBUFFER_1 = 0x00400468,
+ REG_FRAMEBUFFER_2 = 0x00400494,
+};
+
+/// Read a GSP GPU hardware register
+void ReadHWRegs(Service::Interface* self) {
+ static const u32 framebuffer_1[] = {LCD::VRAM_TOP_LEFT_FRAME1, LCD::VRAM_TOP_RIGHT_FRAME1};
+ static const u32 framebuffer_2[] = {LCD::VRAM_TOP_LEFT_FRAME2, LCD::VRAM_TOP_RIGHT_FRAME2};
+
+ u32* cmd_buff = (u32*)HLE::GetPointer(HLE::CMD_BUFFER_ADDR + Service::kCommandHeaderOffset);
+ u32 reg_addr = cmd_buff[1];
+ u32 size = cmd_buff[2];
+ u32* dst = (u32*)Memory::GetPointer(cmd_buff[0x41]);
+
+ switch (reg_addr) {
+
+ // Top framebuffer 1 addresses
+ case REG_FRAMEBUFFER_1:
+ memcpy(dst, framebuffer_1, size);
+ break;
+
+ // Top framebuffer 2 addresses
+ case REG_FRAMEBUFFER_2:
+ memcpy(dst, framebuffer_1, size);
+ break;
+
+ default:
+ ERROR_LOG(OSHLE, "GSP_GPU::ReadHWRegs unknown register read at address %08X", reg_addr);
+ }
+
+}
+
void RegisterInterruptRelayQueue(Service::Interface* self) {
u32* cmd_buff = (u32*)HLE::GetPointer(HLE::CMD_BUFFER_ADDR + Service::kCommandHeaderOffset);
u32 flags = cmd_buff[1];
@@ -26,7 +62,7 @@ const Interface::FunctionInfo FunctionTable[] = {
{0x00010082, NULL, "WriteHWRegs"},
{0x00020084, NULL, "WriteHWRegsWithMask"},
{0x00030082, NULL, "WriteHWRegRepeat"},
- {0x00040080, NULL, "ReadHWRegs"},
+ {0x00040080, ReadHWRegs, "ReadHWRegs"},
{0x00050200, NULL, "SetBufferSwap"},
{0x00060082, NULL, "SetCommandList"},
{0x000700C2, NULL, "RequestDma"},