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authorLioncash <mathew1800@gmail.com>2015-05-31 11:32:46 +0200
committerLioncash <mathew1800@gmail.com>2015-06-01 03:51:25 +0200
commit85b1dddda12ebe339cfc462845f899546ffabe41 (patch)
tree9430ae8fad554140f7943d2d97c2dc9f297bd0b4 /src/core
parentarm_dyncom_thumb: Implement SXTH, SXTB, UXTH, and UXTB. (diff)
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Diffstat (limited to 'src/core')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_thumb.cpp13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_thumb.cpp b/src/core/arm/dyncom/arm_dyncom_thumb.cpp
index 270d966b2..897bb0460 100644
--- a/src/core/arm/dyncom/arm_dyncom_thumb.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_thumb.cpp
@@ -287,6 +287,19 @@ tdstate thumb_translate(u32 addr, u32 instr, u32* ainstr, u32* inst_size) {
*ainstr = subset[BITS(tinstr, 6, 7)] // base
| (BITS(tinstr, 0, 2) << 12) // Rd
| BITS(tinstr, 3, 5); // Rm
+ } else if ((tinstr & 0x0F00) == 0x600) {
+ if (BIT(tinstr, 5) == 0) {
+ // SETEND
+ *ainstr = 0xF1010000 // base
+ | (BIT(tinstr, 3) << 9); // endian specifier
+ } else {
+ // CPS
+ *ainstr = 0xF1080000 // base
+ | (BIT(tinstr, 0) << 6) // fiq bit
+ | (BIT(tinstr, 1) << 7) // irq bit
+ | (BIT(tinstr, 2) << 8) // abort bit
+ | (BIT(tinstr, 4) << 18); // enable bit
+ }
} else if ((tinstr & 0x0F00) == 0x0a00) {
static const ARMword subset[3] = {
0xE6BF0F30, // REV