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authorbunnei <bunneidev@gmail.com>2017-09-30 20:16:39 +0200
committerbunnei <bunneidev@gmail.com>2017-09-30 20:34:03 +0200
commit6377585edb43009e464d4c04b4a35720b5f9d020 (patch)
tree432d8ef516d1dc4a5772bead7e9b47f67468b554 /src/core
parentnso: Refactor and allocate .bss section. (diff)
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Diffstat (limited to 'src/core')
-rw-r--r--src/core/arm/arm_interface.h7
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic.cpp14
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic.h2
-rw-r--r--src/core/arm/dyncom/arm_dyncom.cpp7
-rw-r--r--src/core/arm/dyncom/arm_dyncom.h2
5 files changed, 32 insertions, 0 deletions
diff --git a/src/core/arm/arm_interface.h b/src/core/arm/arm_interface.h
index b52228476..f613556dd 100644
--- a/src/core/arm/arm_interface.h
+++ b/src/core/arm/arm_interface.h
@@ -22,6 +22,9 @@ public:
u64 fpu_registers[64];
u64 fpscr;
u64 fpexc;
+
+ // TODO(bunnei): Fix once we have proper support for tpidrro_el0, etc. in the JIT
+ VAddr tls_address;
};
/**
@@ -121,6 +124,10 @@ public:
*/
virtual void SetCP15Register(CP15Register reg, u32 value) = 0;
+ virtual VAddr GetTlsAddress() const = 0;
+
+ virtual void SetTlsAddress(VAddr address) = 0;
+
/**
* Advance the CPU core by the specified number of ticks (e.g. to simulate CPU execution time)
* @param ticks Number of ticks to advance the CPU core
diff --git a/src/core/arm/dynarmic/arm_dynarmic.cpp b/src/core/arm/dynarmic/arm_dynarmic.cpp
index 3da968344..0ea1d76e4 100644
--- a/src/core/arm/dynarmic/arm_dynarmic.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic.cpp
@@ -157,6 +157,14 @@ void ARM_Dynarmic::SetCP15Register(CP15Register reg, u32 value) {
interpreter_state->CP15[reg] = value;
}
+VAddr ARM_Dynarmic::GetTlsAddress() const {
+ return jit->TlsAddr();
+}
+
+void ARM_Dynarmic::SetTlsAddress(VAddr address) {
+ jit->TlsAddr() = address;
+}
+
void ARM_Dynarmic::AddTicks(u64 ticks) {
down_count -= ticks;
if (down_count < 0) {
@@ -185,6 +193,9 @@ void ARM_Dynarmic::SaveContext(ARM_Interface::ThreadContext& ctx) {
ctx.fpscr = jit->Fpscr();
ctx.fpexc = interpreter_state->VFP[VFP_FPEXC];
+
+ // TODO(bunnei): Fix once we have proper support for tpidrro_el0, etc. in the JIT
+ ctx.tls_address = jit->TlsAddr();
}
void ARM_Dynarmic::LoadContext(const ARM_Interface::ThreadContext& ctx) {
@@ -198,6 +209,9 @@ void ARM_Dynarmic::LoadContext(const ARM_Interface::ThreadContext& ctx) {
jit->SetFpscr(ctx.fpscr);
interpreter_state->VFP[VFP_FPEXC] = ctx.fpexc;
+
+ // TODO(bunnei): Fix once we have proper support for tpidrro_el0, etc. in the JIT
+ jit->TlsAddr() = ctx.tls_address;
}
void ARM_Dynarmic::PrepareReschedule() {
diff --git a/src/core/arm/dynarmic/arm_dynarmic.h b/src/core/arm/dynarmic/arm_dynarmic.h
index f77548d0f..fcdc1c0e0 100644
--- a/src/core/arm/dynarmic/arm_dynarmic.h
+++ b/src/core/arm/dynarmic/arm_dynarmic.h
@@ -26,6 +26,8 @@ public:
void SetCPSR(u32 cpsr) override;
u32 GetCP15Register(CP15Register reg) override;
void SetCP15Register(CP15Register reg, u32 value) override;
+ VAddr GetTlsAddress() const override;
+ void SetTlsAddress(VAddr address) override;
void AddTicks(u64 ticks) override;
diff --git a/src/core/arm/dyncom/arm_dyncom.cpp b/src/core/arm/dyncom/arm_dyncom.cpp
index 1c55496b5..99758fc2a 100644
--- a/src/core/arm/dyncom/arm_dyncom.cpp
+++ b/src/core/arm/dyncom/arm_dyncom.cpp
@@ -73,6 +73,13 @@ void ARM_DynCom::SetCP15Register(CP15Register reg, u32 value) {
state->CP15[reg] = value;
}
+VAddr ARM_DynCom::GetTlsAddress() const {
+ return {};
+}
+
+void ARM_DynCom::SetTlsAddress(VAddr /*address*/) {
+}
+
void ARM_DynCom::AddTicks(u64 ticks) {
down_count -= ticks;
if (down_count < 0)
diff --git a/src/core/arm/dyncom/arm_dyncom.h b/src/core/arm/dyncom/arm_dyncom.h
index 90cc56c41..44e674ae2 100644
--- a/src/core/arm/dyncom/arm_dyncom.h
+++ b/src/core/arm/dyncom/arm_dyncom.h
@@ -29,6 +29,8 @@ public:
void SetCPSR(u32 cpsr) override;
u32 GetCP15Register(CP15Register reg) override;
void SetCP15Register(CP15Register reg, u32 value) override;
+ VAddr GetTlsAddress() const override;
+ void SetTlsAddress(VAddr address) override;
void AddTicks(u64 ticks) override;