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authorjam1garner <8260240+jam1garner@users.noreply.github.com>2021-11-22 03:24:07 +0100
committerjam1garner <8260240+jam1garner@users.noreply.github.com>2021-11-22 04:44:13 +0100
commit4d9c9e567ef6c44967b639471613a0328dcbf833 (patch)
tree974cefabf3a1f3edec5ff0f4056b4601dc893b98 /src/core
parentarm: dynarmic: Implement icache op handling for 'ic iallu' instruction (diff)
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Diffstat (limited to 'src/core')
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_64.cpp19
1 files changed, 9 insertions, 10 deletions
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
index 8fe83413c..56836bd05 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
@@ -88,22 +88,21 @@ public:
void InstructionCacheOperationRaised(Dynarmic::A64::InstructionCacheOperation op,
VAddr value) override {
- constexpr u64 ICACHE_LINE_SIZE = 64;
- u64 cache_line_start;
-
switch (op) {
- case Dynarmic::A64::InstructionCacheOperation::InvalidateByVAToPoU:
- cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
- parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE);
- return;
+ case Dynarmic::A64::InstructionCacheOperation::InvalidateByVAToPoU: {
+ static constexpr u64 ICACHE_LINE_SIZE = 64;
+ const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
+ parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE);
+ break;
+ }
case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
parent.ClearInstructionCache();
- return;
-
+ break;
case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
default:
- LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation");
+ LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation: {}", op);
+ break;
}
}