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| author | bunnei <bunneidev@gmail.com> | 2015-01-07 22:49:30 +0100 |
|---|---|---|
| committer | bunnei <bunneidev@gmail.com> | 2015-01-07 22:49:30 +0100 |
| commit | 4c583732f2eff967e4ac5e717a4ed4d8b5a0000f (patch) | |
| tree | 58438c25a42562b758aa523f9683aa3d0bb6bbba /src/core | |
| parent | Merge pull request #425 from Subv/coretiming (diff) | |
| parent | dyncom: Fix SMULWB/SMULWT (diff) | |
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Diffstat (limited to 'src/core')
| -rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index 426fc6474..7c710ccde 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp @@ -5891,16 +5891,13 @@ unsigned InterpreterMainLoop(ARMul_State* state) { SMULW_INST: { - if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) { - smlad_inst *inst_cream = (smlad_inst *)inst_base->component; - int64_t rm = RM; - int64_t rn = RN; - if (inst_cream->m) - rm = BITS(rm, 16, 31); - else - rm = BITS(rm, 0, 15); - int64_t rst = rm * rn; - RD = BITS(rst, 16, 47); + if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { + smlad_inst* const inst_cream = (smlad_inst*)inst_base->component; + + s16 rm = (inst_cream->m == 1) ? ((RM >> 16) & 0xFFFF) : (RM & 0xFFFF); + + s64 result = (s64)rm * (s64)(s32)RN; + RD = BITS(result, 16, 47); } cpu->Reg[15] += GET_INST_SIZE(cpu); INC_PC(sizeof(smlad_inst)); |