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authorLioncash <mathew1800@gmail.com>2014-12-15 05:00:29 +0100
committerLioncash <mathew1800@gmail.com>2014-12-15 05:00:31 +0100
commit2b0acd36e19f27720b2740efbe68d0f7598ee5c5 (patch)
treed7ae9aa08cc1f962149340f924e1a90a79a28572 /src/core
parentMerge pull request #276 from lioncash/decrappify (diff)
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Diffstat (limited to 'src/core')
-rw-r--r--src/core/arm/interpreter/armemu.cpp24
1 files changed, 12 insertions, 12 deletions
diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp
index ec40881f8..33ebc7986 100644
--- a/src/core/arm/interpreter/armemu.cpp
+++ b/src/core/arm/interpreter/armemu.cpp
@@ -6101,18 +6101,18 @@ L_stm_s_takeabort:
return 1;
}
- case 0x6c:
- if ((instr & 0xf03f0) == 0xf0070) { //uxtb16
- u8 src1 = BITS(0, 3);
- u8 tar = BITS(12, 15);
- u32 base = state->Reg[src1];
- u32 shamt = BITS(9,10)* 8;
- u32 in = ((base << (32 - shamt)) | (base >> shamt));
- state->Reg[tar] = in & 0x00FF00FF;
- return 1;
- } else
- printf ("Unhandled v6 insn: uxtab16\n");
- break;
+ case 0x6c:
+ if ((instr & 0xf03f0) == 0xf0070) { //uxtb16
+ u8 rm_idx = BITS(0, 3);
+ u8 rd_idx = BITS(12, 15);
+ u32 rm_val = state->Reg[rm_idx];
+ u32 rotation = BITS(10, 11) * 8;
+ u32 in = ((rm_val << (32 - rotation)) | (rm_val >> rotation));
+ state->Reg[rd_idx] = in & 0x00FF00FF;
+ return 1;
+ } else
+ printf ("Unhandled v6 insn: uxtab16\n");
+ break;
case 0x6e: {
ARMword Rm;
int ror = -1;