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authorLiam <byteslice@airmail.cc>2023-12-19 18:51:19 +0100
committerLiam <byteslice@airmail.cc>2023-12-19 18:51:19 +0100
commita94721fde0eb716e6c70da285a320b9b96c0c292 (patch)
tree5a8de4ca091e3a341d2a3cb6aa6f1d84e1fe94c1 /src/core/arm
parentMerge pull request #12382 from liamwhite/image-limit (diff)
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Diffstat (limited to 'src/core/arm')
-rw-r--r--src/core/arm/nce/interpreter_visitor.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/core/arm/nce/interpreter_visitor.cpp b/src/core/arm/nce/interpreter_visitor.cpp
index 8e81c66a5..ec373fdf2 100644
--- a/src/core/arm/nce/interpreter_visitor.cpp
+++ b/src/core/arm/nce/interpreter_visitor.cpp
@@ -249,6 +249,7 @@ bool InterpreterVisitor::LDR_lit_fpsimd(Imm<2> opc, Imm<19> imm19, Vec Vt) {
return false;
}
+ // Size in bytes
const u64 size = 4 << opc.ZeroExtend();
const u64 offset = imm19.SignExtend<u64>() << 2;
const u64 address = this->GetPc() + offset;
@@ -530,7 +531,7 @@ bool InterpreterVisitor::SIMDImmediate(bool wback, bool postindex, size_t scale,
}
case MemOp::Load: {
u128 data{};
- m_memory.ReadBlock(address, &data, datasize);
+ m_memory.ReadBlock(address, &data, datasize / 8);
this->SetVec(Vt, data);
break;
}