diff options
author | archshift <gh@archshift.com> | 2016-06-11 03:26:42 +0200 |
---|---|---|
committer | archshift <gh@archshift.com> | 2016-06-11 03:35:57 +0200 |
commit | 5297f5dfc914ebdfb027edb964bc141d01be9c6a (patch) | |
tree | b7d56fcc116c7d7b7f96a324a4e2b4950d210aa5 /src/core/arm/dyncom/arm_dyncom_interpreter.cpp | |
parent | arm_dyncom_interpreter.cpp: #include translation info from inc files (diff) | |
download | yuzu-5297f5dfc914ebdfb027edb964bc141d01be9c6a.tar yuzu-5297f5dfc914ebdfb027edb964bc141d01be9c6a.tar.gz yuzu-5297f5dfc914ebdfb027edb964bc141d01be9c6a.tar.bz2 yuzu-5297f5dfc914ebdfb027edb964bc141d01be9c6a.tar.lz yuzu-5297f5dfc914ebdfb027edb964bc141d01be9c6a.tar.xz yuzu-5297f5dfc914ebdfb027edb964bc141d01be9c6a.tar.zst yuzu-5297f5dfc914ebdfb027edb964bc141d01be9c6a.zip |
Diffstat (limited to 'src/core/arm/dyncom/arm_dyncom_interpreter.cpp')
-rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index b45a6cd64..0e38bef22 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp @@ -24,7 +24,7 @@ #include "core/gdbstub/gdbstub.h" -enum { +enum class TransExtData { COND = (1 << 0), NON_BRANCH = (1 << 1), DIRECT_BRANCH = (1 << 2), @@ -853,14 +853,14 @@ static int InterpreterTranslateBlock(ARMul_State* cpu, int& bb_start, u32 addr) // Go on next, until terminal instruction // Save start addr of basicblock in CreamCache ARM_INST_PTR inst_base = nullptr; - int ret = NON_BRANCH; + TransExtData ret = TransExtData::NON_BRANCH; int size = 0; // instruction size of basic block bb_start = top; u32 phys_addr = addr; u32 pc_start = cpu->Reg[15]; - while (ret == NON_BRANCH) { + while (ret == TransExtData::NON_BRANCH) { unsigned int inst_size = InterpreterTranslateInstruction(cpu, phys_addr, inst_base); size++; @@ -868,7 +868,7 @@ static int InterpreterTranslateBlock(ARMul_State* cpu, int& bb_start, u32 addr) phys_addr += inst_size; if ((phys_addr & 0xfff) == 0) { - inst_base->br = END_OF_PAGE; + inst_base->br = TransExtData::END_OF_PAGE; } ret = inst_base->br; }; @@ -889,8 +889,8 @@ static int InterpreterTranslateSingle(ARMul_State* cpu, int& bb_start, u32 addr) InterpreterTranslateInstruction(cpu, phys_addr, inst_base); - if (inst_base->br == NON_BRANCH) { - inst_base->br = SINGLE_STEP; + if (inst_base->br == TransExtData::NON_BRANCH) { + inst_base->br = TransExtData::SINGLE_STEP; } cpu->instruction_cache[pc_start] = bb_start; @@ -935,7 +935,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) { #define SET_PC (cpu->Reg[15] = cpu->Reg[15] + 8 + inst_cream->signed_immed_24) #define SHIFTER_OPERAND inst_cream->shtop_func(cpu, inst_cream->shifter_operand) - #define FETCH_INST if (inst_base->br != NON_BRANCH) goto DISPATCH; \ + #define FETCH_INST if (inst_base->br != TransExtData::NON_BRANCH) goto DISPATCH; \ inst_base = (arm_inst *)&inst_buf[ptr] #define INC_PC(l) ptr += sizeof(arm_inst) + l |