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authorTony Wasserka <NeoBrainX@gmail.com>2014-06-04 18:30:23 +0200
committerTony Wasserka <NeoBrainX@gmail.com>2014-07-23 00:33:08 +0200
commitbaf0aa04f50dff257b57fa78786e53b97c1e6abb (patch)
tree3dc92a276f58d1099eb19dd2b5fcb52c69a8da9a
parentGPU: Add proper framebuffer register handling. (diff)
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-rw-r--r--src/core/hle/service/gsp.cpp8
-rw-r--r--src/core/hle/service/gsp.h2
-rw-r--r--src/core/hw/gpu.cpp56
-rw-r--r--src/core/hw/gpu.h26
4 files changed, 89 insertions, 3 deletions
diff --git a/src/core/hle/service/gsp.cpp b/src/core/hle/service/gsp.cpp
index fea521891..5baa7a7a2 100644
--- a/src/core/hle/service/gsp.cpp
+++ b/src/core/hle/service/gsp.cpp
@@ -174,6 +174,14 @@ void TriggerCmdReqQueue(Service::Interface* self) {
break;
case GXCommandId::SET_MEMORY_FILL:
+ GPU::Write<u32>(GPU::Registers::MemoryFillStart1, cmd_buff[1] >> 3);
+ GPU::Write<u32>(GPU::Registers::MemoryFillEnd1, cmd_buff[3] >> 3);
+ GPU::Write<u32>(GPU::Registers::MemoryFillSize1, cmd_buff[3] - cmd_buff[1]);
+ GPU::Write<u32>(GPU::Registers::MemoryFillValue1, cmd_buff[2]);
+ GPU::Write<u32>(GPU::Registers::MemoryFillStart2, cmd_buff[4] >> 3);
+ GPU::Write<u32>(GPU::Registers::MemoryFillEnd2, cmd_buff[6] >> 3);
+ GPU::Write<u32>(GPU::Registers::MemoryFillSize2, cmd_buff[6] - cmd_buff[4]);
+ GPU::Write<u32>(GPU::Registers::MemoryFillValue2, cmd_buff[5]);
break;
// TODO: Check if texture copies are implemented correctly..
diff --git a/src/core/hle/service/gsp.h b/src/core/hle/service/gsp.h
index 214de140f..fb50a928a 100644
--- a/src/core/hle/service/gsp.h
+++ b/src/core/hle/service/gsp.h
@@ -14,7 +14,7 @@ namespace GSP_GPU {
enum class GXCommandId : u32 {
REQUEST_DMA = 0x00000000,
SET_COMMAND_LIST_LAST = 0x00000001,
- SET_MEMORY_FILL = 0x00000002, // TODO: Confirm? (lictru uses 0x01000102)
+ SET_MEMORY_FILL = 0x01000102, // TODO: Confirm?
SET_DISPLAY_TRANSFER = 0x00000003,
SET_TEXTURE_COPY = 0x00000004,
SET_COMMAND_LIST_FIRST = 0x00000005,
diff --git a/src/core/hw/gpu.cpp b/src/core/hw/gpu.cpp
index fad3439c8..230a12d46 100644
--- a/src/core/hw/gpu.cpp
+++ b/src/core/hw/gpu.cpp
@@ -84,6 +84,26 @@ const u8* GetFramebufferPointer(const u32 address) {
template <typename T>
inline void Read(T &var, const u32 addr) {
switch (addr) {
+ case Registers::MemoryFillStart1:
+ case Registers::MemoryFillStart2:
+ var = g_regs.memory_fill[(addr - Registers::MemoryFillStart1) / 0x10].address_start;
+ break;
+
+ case Registers::MemoryFillEnd1:
+ case Registers::MemoryFillEnd2:
+ var = g_regs.memory_fill[(addr - Registers::MemoryFillEnd1) / 0x10].address_end;
+ break;
+
+ case Registers::MemoryFillSize1:
+ case Registers::MemoryFillSize2:
+ var = g_regs.memory_fill[(addr - Registers::MemoryFillSize1) / 0x10].size;
+ break;
+
+ case Registers::MemoryFillValue1:
+ case Registers::MemoryFillValue2:
+ var = g_regs.memory_fill[(addr - Registers::MemoryFillValue1) / 0x10].value;
+ break;
+
case Registers::FramebufferTopSize:
var = g_regs.top_framebuffer.size;
break;
@@ -194,6 +214,40 @@ inline void Read(T &var, const u32 addr) {
template <typename T>
inline void Write(u32 addr, const T data) {
switch (static_cast<Registers::Id>(addr)) {
+ case Registers::MemoryFillStart1:
+ case Registers::MemoryFillStart2:
+ g_regs.memory_fill[(addr - Registers::MemoryFillStart1) / 0x10].address_start = data;
+ break;
+
+ case Registers::MemoryFillEnd1:
+ case Registers::MemoryFillEnd2:
+ g_regs.memory_fill[(addr - Registers::MemoryFillEnd1) / 0x10].address_end = data;
+ break;
+
+ case Registers::MemoryFillSize1:
+ case Registers::MemoryFillSize2:
+ g_regs.memory_fill[(addr - Registers::MemoryFillSize1) / 0x10].size = data;
+ break;
+
+ case Registers::MemoryFillValue1:
+ case Registers::MemoryFillValue2:
+ {
+ Registers::MemoryFillConfig& config = g_regs.memory_fill[(addr - Registers::MemoryFillValue1) / 0x10];
+ config.value = data;
+
+ // TODO: Not sure if this check should be done at GSP level instead
+ if (config.address_start) {
+ // TODO: Not sure if this algorithm is correct, particularly because it doesn't use the size member at all
+ u32* start = (u32*)Memory::GetPointer(config.GetStartAddress());
+ u32* end = (u32*)Memory::GetPointer(config.GetEndAddress());
+ for (u32* ptr = start; ptr < end; ++ptr)
+ *ptr = bswap32(config.value); // TODO: This is just a workaround to missing framebuffer format emulation
+
+ DEBUG_LOG(GPU, "MemoryFill from %x to %x", config.GetStartAddress(), config.GetEndAddress());
+ }
+ break;
+ }
+
// TODO: Framebuffer registers!!
case Registers::FramebufferTopSwapBuffers:
g_regs.top_framebuffer.active_fb = data;
@@ -240,8 +294,6 @@ inline void Write(u32 addr, const T data) {
g_regs.display_transfer.output_width * 4);
}
- // Clear previous contents until we implement proper buffer clearing
- memset(source_pointer, 0x20, g_regs.display_transfer.input_width*g_regs.display_transfer.input_height*4);
DEBUG_LOG(GPU, "DisplayTriggerTransfer: %x bytes from %x(%xx%x)-> %x(%xx%x), dst format %x",
g_regs.display_transfer.output_height * g_regs.display_transfer.output_width * 4,
g_regs.display_transfer.GetPhysicalInputAddress(), (int)g_regs.display_transfer.input_width, (int)g_regs.display_transfer.input_height,
diff --git a/src/core/hw/gpu.h b/src/core/hw/gpu.h
index 50c360814..47d7fcb26 100644
--- a/src/core/hw/gpu.h
+++ b/src/core/hw/gpu.h
@@ -14,6 +14,15 @@ static const u32 kFrameTicks = kFrameCycles / 3; ///< Approximate number of i
struct Registers {
enum Id : u32 {
+ MemoryFillStart1 = 0x1EF00010,
+ MemoryFillEnd1 = 0x1EF00014,
+ MemoryFillSize1 = 0x1EF00018,
+ MemoryFillValue1 = 0x1EF0001C,
+ MemoryFillStart2 = 0x1EF00020,
+ MemoryFillEnd2 = 0x1EF00024,
+ MemoryFillSize2 = 0x1EF00028,
+ MemoryFillValue2 = 0x1EF0002C,
+
FramebufferTopSize = 0x1EF0045C,
FramebufferTopLeft1 = 0x1EF00468, // Main LCD, first framebuffer for 3D left
FramebufferTopLeft2 = 0x1EF0046C, // Main LCD, second framebuffer for 3D left
@@ -53,6 +62,23 @@ struct Registers {
RGBA4 = 4,
};
+ struct MemoryFillConfig {
+ u32 address_start;
+ u32 address_end; // ?
+ u32 size;
+ u32 value; // ?
+
+ inline u32 GetStartAddress() const {
+ return address_start * 8;
+ }
+
+ inline u32 GetEndAddress() const {
+ return address_end * 8;
+ }
+ };
+
+ MemoryFillConfig memory_fill[2];
+
// TODO: Move these into the framebuffer struct
u32 framebuffer_top_left_1;
u32 framebuffer_top_left_2;