From f7edbcd7a3e8f12b2db98220784c6f490e429a5f Mon Sep 17 00:00:00 2001 From: Subv Date: Sun, 19 Aug 2018 14:00:12 -0500 Subject: Shaders/TEXS: Fixed the component mask in the TEXS instruction. Previously we could end up with a TEXS that didn't write any outputs, this was wrong. --- src/video_core/engines/shader_bytecode.h | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 8ae0e6df2..096de9632 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h @@ -12,6 +12,7 @@ #include +#include "common/assert.h" #include "common/bit_field.h" #include "common/common_types.h" @@ -446,16 +447,20 @@ union Instruction { } bool IsComponentEnabled(size_t component) const { - static constexpr std::array, 4> mask_lut{ - {{}, - {0x1, 0x2, 0x4, 0x8, 0x3}, - {0x1, 0x2, 0x4, 0x8, 0x3, 0x9, 0xa, 0xc}, - {0x7, 0xb, 0xd, 0xe, 0xf}}}; + static constexpr std::array, 4> mask_lut{{ + {}, + {0x1, 0x2, 0x4, 0x8, 0x3, 0x9, 0xa, 0xc}, + {0x1, 0x2, 0x4, 0x8, 0x3, 0x9, 0xa, 0xc}, + {0x7, 0xb, 0xd, 0xe, 0xf}, + }}; size_t index{gpr0.Value() != Register::ZeroIndex ? 1U : 0U}; index |= gpr28.Value() != Register::ZeroIndex ? 2 : 0; - return ((1ull << component) & mask_lut[index][component_mask_selector]) != 0; + u32 mask = mask_lut[index][component_mask_selector]; + // A mask of 0 means this instruction uses an unimplemented mask. + ASSERT(mask != 0); + return ((1ull << component) & mask) != 0; } } texs; -- cgit v1.2.3