From 827bb08c91086e0e24edb82df79c9ed860baf836 Mon Sep 17 00:00:00 2001 From: Subv Date: Wed, 6 Jun 2018 23:53:43 -0500 Subject: GPU: Added registers for the CLEAR_BUFFERS and CLEAR_COLOR methods. --- src/video_core/engines/maxwell_3d.h | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) (limited to 'src/video_core/engines') diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h index ff67f2a58..e264dd4d8 100644 --- a/src/video_core/engines/maxwell_3d.h +++ b/src/video_core/engines/maxwell_3d.h @@ -436,7 +436,12 @@ public: u32 count; } vertex_buffer; - INSERT_PADDING_WORDS(0x99); + INSERT_PADDING_WORDS(1); + + float clear_color[4]; + float clear_depth; + + INSERT_PADDING_WORDS(0x93); struct { u32 address_high; @@ -584,7 +589,21 @@ public: Cull cull; - INSERT_PADDING_WORDS(0x77); + INSERT_PADDING_WORDS(0x2B); + + union { + u32 raw; + BitField<0, 1, u32> Z; + BitField<1, 1, u32> S; + BitField<2, 1, u32> R; + BitField<3, 1, u32> G; + BitField<4, 1, u32> B; + BitField<5, 1, u32> A; + BitField<6, 4, u32> RT; + BitField<10, 11, u32> layer; + } clear_buffers; + + INSERT_PADDING_WORDS(0x4B); struct { u32 query_address_high; @@ -766,6 +785,9 @@ private: /// Handles writes to the macro uploading registers. void ProcessMacroUpload(u32 data); + /// Handles a write to the CLEAR_BUFFERS register. + void ProcessClearBuffers(); + /// Handles a write to the QUERY_GET register. void ProcessQueryGet(); @@ -788,6 +810,8 @@ ASSERT_REG_POSITION(rt, 0x200); ASSERT_REG_POSITION(viewport_transform[0], 0x280); ASSERT_REG_POSITION(viewport, 0x300); ASSERT_REG_POSITION(vertex_buffer, 0x35D); +ASSERT_REG_POSITION(clear_color[0], 0x360); +ASSERT_REG_POSITION(clear_depth, 0x364); ASSERT_REG_POSITION(zeta, 0x3F8); ASSERT_REG_POSITION(vertex_attrib_format[0], 0x458); ASSERT_REG_POSITION(rt_control, 0x487); @@ -803,6 +827,7 @@ ASSERT_REG_POSITION(code_address, 0x582); ASSERT_REG_POSITION(draw, 0x585); ASSERT_REG_POSITION(index_array, 0x5F2); ASSERT_REG_POSITION(cull, 0x646); +ASSERT_REG_POSITION(clear_buffers, 0x674); ASSERT_REG_POSITION(query, 0x6C0); ASSERT_REG_POSITION(vertex_array[0], 0x700); ASSERT_REG_POSITION(independent_blend, 0x780); -- cgit v1.2.3 From be51120d237cb551fae90fbfaebda41669c40403 Mon Sep 17 00:00:00 2001 From: Subv Date: Wed, 6 Jun 2018 23:54:25 -0500 Subject: GPU: Bind and clear the render target when the CLEAR_BUFFERS register is written to. --- src/video_core/engines/maxwell_3d.cpp | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'src/video_core/engines') diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp index 93c43c8cb..78f1c0ea7 100644 --- a/src/video_core/engines/maxwell_3d.cpp +++ b/src/video_core/engines/maxwell_3d.cpp @@ -126,6 +126,10 @@ void Maxwell3D::WriteReg(u32 method, u32 value, u32 remaining_params) { DrawArrays(); break; } + case MAXWELL3D_REG_INDEX(clear_buffers): { + ProcessClearBuffers(); + break; + } case MAXWELL3D_REG_INDEX(query.query_get): { ProcessQueryGet(); break; @@ -415,5 +419,12 @@ bool Maxwell3D::IsShaderStageEnabled(Regs::ShaderStage stage) const { UNREACHABLE(); } +void Maxwell3D::ProcessClearBuffers() { + ASSERT(regs.clear_buffers.R && regs.clear_buffers.G && regs.clear_buffers.B && + regs.clear_buffers.A); + + VideoCore::g_renderer->Rasterizer()->Clear(); +} + } // namespace Engines } // namespace Tegra -- cgit v1.2.3 From c1811ed3d1805e0d0ab536762692e7c0e80f14dc Mon Sep 17 00:00:00 2001 From: Subv Date: Mon, 2 Jul 2018 19:09:03 -0500 Subject: GPU: Support clears that don't clear the color buffer. --- src/video_core/engines/maxwell_3d.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/video_core/engines') diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp index 78f1c0ea7..4d1a79c55 100644 --- a/src/video_core/engines/maxwell_3d.cpp +++ b/src/video_core/engines/maxwell_3d.cpp @@ -420,8 +420,9 @@ bool Maxwell3D::IsShaderStageEnabled(Regs::ShaderStage stage) const { } void Maxwell3D::ProcessClearBuffers() { - ASSERT(regs.clear_buffers.R && regs.clear_buffers.G && regs.clear_buffers.B && - regs.clear_buffers.A); + ASSERT(regs.clear_buffers.R == regs.clear_buffers.G && + regs.clear_buffers.R == regs.clear_buffers.B && + regs.clear_buffers.R == regs.clear_buffers.A); VideoCore::g_renderer->Rasterizer()->Clear(); } -- cgit v1.2.3