From ba02d564f8a0b0167b96f247b6ad9d2bde05b6c8 Mon Sep 17 00:00:00 2001 From: Fernando Sahmkow Date: Sun, 15 Sep 2019 11:48:54 -0400 Subject: Video Core: initial Implementation of InstanceDraw Packaging --- src/video_core/engines/maxwell_3d.cpp | 74 +++++++++++++++++++++++++++++++++++ src/video_core/engines/maxwell_3d.h | 23 ++++++++++- 2 files changed, 96 insertions(+), 1 deletion(-) (limited to 'src/video_core/engines') diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp index c7a3c85a0..48fc1a9e1 100644 --- a/src/video_core/engines/maxwell_3d.cpp +++ b/src/video_core/engines/maxwell_3d.cpp @@ -92,6 +92,10 @@ void Maxwell3D::InitializeRegisterDefaults() { // Some games (like Super Mario Odyssey) assume that SRGB is enabled. regs.framebuffer_srgb = 1; + mme_inline[MAXWELL3D_REG_INDEX(draw.vertex_end_gl)] = true; + mme_inline[MAXWELL3D_REG_INDEX(draw.vertex_begin_gl)] = true; + mme_inline[MAXWELL3D_REG_INDEX(vertex_buffer.count)] = true; + mme_inline[MAXWELL3D_REG_INDEX(index_array.count)] = true; } #define DIRTY_REGS_POS(field_name) (offsetof(Maxwell3D::DirtyRegs, field_name)) @@ -416,6 +420,76 @@ void Maxwell3D::CallMethod(const GPU::MethodCall& method_call) { } } +void Maxwell3D::CallMethodFromMME(const GPU::MethodCall& method_call) { + const u32 method = method_call.method; + if (mme_inline[method]) { + regs.reg_array[method] = method_call.argument; + if (method == MAXWELL3D_REG_INDEX(vertex_buffer.count) || + method == MAXWELL3D_REG_INDEX(index_array.count)) { + MMMEDrawMode expected_mode = method == MAXWELL3D_REG_INDEX(vertex_buffer.count) + ? MMMEDrawMode::Array + : MMMEDrawMode::Indexed; + u32 count = method_call.argument; + while (true) { + if (mme_draw.current_mode == MMMEDrawMode::Undefined) { + mme_draw.current_mode = expected_mode; + mme_draw.current_count = count; + mme_draw.instance_count = 1; + break; + } else { + if (mme_draw.current_mode == expected_mode && count == mme_draw.current_count) { + mme_draw.instance_count++; + break; + } else { + FlushMMEInlineDraw(); + } + } + } + } + } else { + if (mme_draw.current_mode != MMMEDrawMode::Undefined) { + FlushMMEInlineDraw(); + } + CallMethod(method_call); + } +} + +void Maxwell3D::FlushMMEInlineDraw() { + LOG_DEBUG(HW_GPU, "called, topology={}, count={}", static_cast(regs.draw.topology.Value()), + regs.vertex_buffer.count); + ASSERT_MSG(!(regs.index_array.count && regs.vertex_buffer.count), "Both indexed and direct?"); + + auto debug_context = system.GetGPUDebugContext(); + + if (debug_context) { + debug_context->OnEvent(Tegra::DebugContext::Event::IncomingPrimitiveBatch, nullptr); + } + + // Both instance configuration registers can not be set at the same time. + ASSERT_MSG(!regs.draw.instance_next || !regs.draw.instance_cont, + "Illegal combination of instancing parameters"); + + const bool is_indexed = mme_draw.current_mode == MMMEDrawMode::Indexed; + rasterizer.AccelerateDrawMultiBatch(is_indexed); + + if (debug_context) { + debug_context->OnEvent(Tegra::DebugContext::Event::FinishedPrimitiveBatch, nullptr); + } + + // TODO(bunnei): Below, we reset vertex count so that we can use these registers to determine if + // the game is trying to draw indexed or direct mode. This needs to be verified on HW still - + // it's possible that it is incorrect and that there is some other register used to specify the + // drawing mode. + if (is_indexed) { + regs.index_array.count = 0; + } else { + regs.vertex_buffer.count = 0; + } + mme_draw.current_mode = MMMEDrawMode::Undefined; + mme_draw.current_count = 0; + mme_draw.instance_count = 0; +} + void Maxwell3D::ProcessMacroUpload(u32 data) { ASSERT_MSG(regs.macros.upload_address < macro_memory.size(), "upload_address exceeded macro_memory size!"); diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h index e5ec90717..1547d930e 100644 --- a/src/video_core/engines/maxwell_3d.h +++ b/src/video_core/engines/maxwell_3d.h @@ -811,8 +811,9 @@ public: INSERT_PADDING_WORDS(0x21); u32 vb_element_base; + u32 vb_base_instance; - INSERT_PADDING_WORDS(0x36); + INSERT_PADDING_WORDS(0x35); union { BitField<0, 1, u32> c0; @@ -1238,6 +1239,11 @@ public: /// Write the value to the register identified by method. void CallMethod(const GPU::MethodCall& method_call); + /// Write the value to the register identified by method. + void CallMethodFromMME(const GPU::MethodCall& method_call); + + void FlushMMEInlineDraw(); + /// Given a Texture Handle, returns the TSC and TIC entries. Texture::FullTextureInfo GetTextureInfo(const Texture::TextureHandle tex_handle, std::size_t offset) const; @@ -1263,6 +1269,18 @@ public: return execute_on; } + enum class MMMEDrawMode : u32 { + Undefined, + Array, + Indexed, + }; + + struct MMEDrawState { + MMMEDrawMode current_mode{MMMEDrawMode::Undefined}; + u32 current_count; + u32 instance_count; + } mme_draw; + private: void InitializeRegisterDefaults(); @@ -1275,6 +1293,8 @@ private: /// Start offsets of each macro in macro_memory std::array macro_positions = {}; + std::array mme_inline{}; + /// Memory for macro code MacroMemory macro_memory; @@ -1402,6 +1422,7 @@ ASSERT_REG_POSITION(stencil_front_mask, 0x4E7); ASSERT_REG_POSITION(frag_color_clamp, 0x4EA); ASSERT_REG_POSITION(screen_y_control, 0x4EB); ASSERT_REG_POSITION(vb_element_base, 0x50D); +ASSERT_REG_POSITION(vb_base_instance, 0x50E); ASSERT_REG_POSITION(clip_distance_enabled, 0x544); ASSERT_REG_POSITION(point_size, 0x546); ASSERT_REG_POSITION(zeta_enable, 0x54E); -- cgit v1.2.3