From 579000e747413b9af3860c0b92e143d4ddc44e36 Mon Sep 17 00:00:00 2001 From: Subv Date: Sat, 17 Mar 2018 13:55:42 -0500 Subject: GPU: Corrected the parameter documentation for the SetShader macro call. Register 0xE24 is actually a macro that sets some shader parameters in the register structure. Macros are uploaded to the GPU at startup and have their own ISA, we'll probably write an interpreter for this in the future. --- src/video_core/engines/maxwell_3d.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src/video_core/engines/maxwell_3d.h') diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h index c979d4e61..47df43c97 100644 --- a/src/video_core/engines/maxwell_3d.h +++ b/src/video_core/engines/maxwell_3d.h @@ -139,9 +139,9 @@ public: INSERT_PADDING_WORDS(0x5D0); struct { - u32 shader_code_call; - u32 shader_code_args; - } shader_code; + u32 set_shader_call; + u32 set_shader_args; + } set_shader; INSERT_PADDING_WORDS(0x10); }; std::array reg_array; @@ -154,8 +154,8 @@ public: struct ShaderInfo { Regs::ShaderType type; Regs::ShaderProgram program; - GPUVAddr begin_address; - GPUVAddr end_address; + GPUVAddr address; + GPUVAddr cb_address; }; std::array shaders; @@ -194,7 +194,7 @@ ASSERT_REG_POSITION(query, 0x6C0); ASSERT_REG_POSITION(vertex_array[0], 0x700); ASSERT_REG_POSITION(vertex_array_limit[0], 0x7C0); ASSERT_REG_POSITION(shader_config[0], 0x800); -ASSERT_REG_POSITION(shader_code, 0xE24); +ASSERT_REG_POSITION(set_shader, 0xE24); #undef ASSERT_REG_POSITION -- cgit v1.2.3