| Commit message (Collapse) | Author | Files | Lines |
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and wip nv thread shuffle impl
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Fix for SULD.D
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along with some more cleanup/oversight fixes
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and more cleanup
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needed for HW:AoC.
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along with some other misc changes and fixes
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and add some more separation in the shader for better debugability when dumped
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and implement misc getters
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SSBU now working
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and missed a diff in emit_glsl relating to var alloc ref counting
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fixes font rendering issues as these were used to index into the ssbos
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to fix Loop control flow.
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plus some other misc additions/changed
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and many other misc implementations
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Logic for ordered/unordered ops was wrong.
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based on glasm with some tweaks
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Also add a setting for enable Nsight Aftermath.
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The sign bit on integers of size < 32 was not properly preserved in casts
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BitCast U32 to S32 before converting to float on drivers with broken
signed operations.
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"Negative" offsets don't exist. They are shown as such due to a bug in
nvdisasm.
Unaligned offsets have been proved to read the aligned offset. For
example, when reading an U32, if the offset is 6, the offset read will
be 4.
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Fixes Ori and the Blind Forest's menu on GLASM. For some reason
(probably high level optimizations) it is not sanitized on SPIR-V for
OpenGL. Vulkan is unaffected by this change.
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Causes regressions on Bowser's Fury.
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Add support for null registers. These are used when an instruction has
no usages.
This comes handy when an instruction is only used for its CC value, with
the caveat of having to invalidate all pseudo-instructions before
defining the instruction itself in the register allocator. This commits
changes this.
Workaround a bug on Nvidia's condition codes conditional execution using
branches.
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Reorder them to the bottom of the file for readability.
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With this, Luigi's Mansion's sand renders properly.
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Immediate condition refs where not handled correctly. Just move the
value for now.
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Fixes the identity removal pass.
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Remove lod clamp from texture instructions with lod, as this is not
needed (nor supported).
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Fixes members of unnamed union not being accessible, and one function
without a declaration.
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Silence unused variable warning
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This commit regresses VertexA shaders, their transformation pass has to
be adapted to the new control flow.
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StorageAtomicExchangeU64 is failing test seemingly due to failure storing 64-bit
result into the register
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Use a struct constructor to serialize register allocation arguments to
ensure registers are allocated in the same order regardless of the
compiler used.
The A and B functions can be called in any order when passed as
arguments to "foo":
foo(A(), B())
But the order is guaranteed for curly-braced constructor calls in
classes:
Foo{A(), B()}
Use this to get consistent behavior.
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also fixes ADD and SUB to use U modifier
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Along with implementations of common instructions along the way
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This is enabled by an extension instead of the capability.
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Workaround bug on Nvidia's OpenGL SPIR-V compiler when using unsigned
texture offsets.
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Workaround more bugs on Nvidia's OpenGL SPIR-V compiler.
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Worksaround a bug on Nvidia's OpenGL SPIR-V compiler where names are
used for name matching.
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When we can't track the SSBO origin of a global memory instruction,
leave it as a global memory operation and assume these pointers are in
the NVN storage buffer slots, then apply a linear search in the shader's
runtime.
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Fix two bugs in BFI.
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Mostly fixing unused *, implicit conversion, braced scalar init,
fpermissive, and some others.
Some Clang errors likely remain in video_core, and std::ranges is still
a pertinent issue in shader_recompiler
shader_recompiler: cmake: Force bracket depth to 1024 on Clang
Increases the maximum fold expression depth
thread_worker: Include condition_variable
Don't use list initializers in control flow
Co-authored-by: ReinUsesLisp <reinuseslisp@airmail.cc>
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It may generate better code on some compilers and it's easier to handle.
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This is needed because pseudo-instructions where invalidated.
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Also fix oversight with adding SignedZeroInfNanPreserve execution mode.
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And add a const in FCMP
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still need to configure some settings for NV denorm flush and intel NaN
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