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Diffstat (limited to 'src/video_core/renderer_opengl/gl_shader_decompiler.cpp')
-rw-r--r--src/video_core/renderer_opengl/gl_shader_decompiler.cpp238
1 files changed, 183 insertions, 55 deletions
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
index dcf6941b0..09b003c59 100644
--- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
+++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
@@ -3,12 +3,12 @@
// Refer to the license.txt file included.
#include <map>
+#include <optional>
#include <set>
#include <string>
#include <string_view>
#include <unordered_set>
-#include <boost/optional.hpp>
#include <fmt/format.h>
#include "common/assert.h"
@@ -144,7 +144,7 @@ private:
for (u32 offset = begin; offset != end && offset != PROGRAM_END; ++offset) {
const Instruction instr = {program_code[offset]};
if (const auto opcode = OpCode::Decode(instr)) {
- switch (opcode->GetId()) {
+ switch (opcode->get().GetId()) {
case OpCode::Id::EXIT: {
// The EXIT instruction can be predicated, which means that the shader can
// conditionally end on this instruction. We have to consider the case where the
@@ -373,6 +373,7 @@ public:
if (sets_cc) {
const std::string zero_condition = "( " + ConvertIntegerSize(value, size) + " == 0 )";
SetInternalFlag(InternalFlag::ZeroFlag, zero_condition);
+ LOG_WARNING(HW_GPU, "Control Codes Imcomplete.");
}
}
@@ -430,7 +431,7 @@ public:
*/
void SetRegisterToInputAttibute(const Register& reg, u64 elem, Attribute::Index attribute,
const Tegra::Shader::IpaMode& input_mode,
- boost::optional<Register> vertex = {}) {
+ std::optional<Register> vertex = {}) {
const std::string dest = GetRegisterAsFloat(reg);
const std::string src = GetInputAttribute(attribute, input_mode, vertex) + GetSwizzle(elem);
shader.AddLine(dest + " = " + src + ';');
@@ -807,10 +808,10 @@ private:
/// Generates code representing an input attribute register.
std::string GetInputAttribute(Attribute::Index attribute,
const Tegra::Shader::IpaMode& input_mode,
- boost::optional<Register> vertex = {}) {
+ std::optional<Register> vertex = {}) {
auto GeometryPass = [&](const std::string& name) {
if (stage == Maxwell3D::Regs::ShaderStage::Geometry && vertex) {
- return "gs_" + name + '[' + GetRegisterAsInteger(vertex.value(), 0, false) + ']';
+ return "gs_" + name + '[' + GetRegisterAsInteger(*vertex, 0, false) + ']';
}
return name;
};
@@ -1465,7 +1466,7 @@ private:
}
shader.AddLine(
- fmt::format("// {}: {} (0x{:016x})", offset, opcode->GetName(), instr.value));
+ fmt::format("// {}: {} (0x{:016x})", offset, opcode->get().GetName(), instr.value));
using Tegra::Shader::Pred;
ASSERT_MSG(instr.pred.full_pred != Pred::NeverExecute,
@@ -1473,7 +1474,7 @@ private:
// Some instructions (like SSY) don't have a predicate field, they are always
// unconditionally executed.
- bool can_be_predicated = OpCode::IsPredicatedInstruction(opcode->GetId());
+ bool can_be_predicated = OpCode::IsPredicatedInstruction(opcode->get().GetId());
if (can_be_predicated && instr.pred.pred_index != static_cast<u64>(Pred::UnusedIndex)) {
shader.AddLine("if (" +
@@ -1483,7 +1484,7 @@ private:
++shader.scope;
}
- switch (opcode->GetType()) {
+ switch (opcode->get().GetType()) {
case OpCode::Type::Arithmetic: {
std::string op_a = regs.GetRegisterAsFloat(instr.gpr8);
@@ -1500,7 +1501,7 @@ private:
}
}
- switch (opcode->GetId()) {
+ switch (opcode->get().GetId()) {
case OpCode::Id::MOV_C:
case OpCode::Id::MOV_R: {
// MOV does not have neither 'abs' nor 'neg' bits.
@@ -1525,6 +1526,10 @@ private:
regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " * " + op_b, 1, 1,
instr.alu.saturate_d, 0, true);
+ if (instr.generates_cc) {
+ LOG_CRITICAL(HW_GPU, "FMUL Generates an unhandled Control Code");
+ UNREACHABLE();
+ }
break;
}
case OpCode::Id::FADD_C:
@@ -1535,6 +1540,10 @@ private:
regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " + " + op_b, 1, 1,
instr.alu.saturate_d, 0, true);
+ if (instr.generates_cc) {
+ LOG_CRITICAL(HW_GPU, "FADD Generates an unhandled Control Code");
+ UNREACHABLE();
+ }
break;
}
case OpCode::Id::MUFU: {
@@ -1588,6 +1597,10 @@ private:
'(' + condition + ") ? min(" + parameters + ") : max(" +
parameters + ')',
1, 1, false, 0, true);
+ if (instr.generates_cc) {
+ LOG_CRITICAL(HW_GPU, "FMNMX Generates an unhandled Control Code");
+ UNREACHABLE();
+ }
break;
}
case OpCode::Id::RRO_C:
@@ -1600,14 +1613,15 @@ private:
break;
}
default: {
- LOG_CRITICAL(HW_GPU, "Unhandled arithmetic instruction: {}", opcode->GetName());
+ LOG_CRITICAL(HW_GPU, "Unhandled arithmetic instruction: {}",
+ opcode->get().GetName());
UNREACHABLE();
}
}
break;
}
case OpCode::Type::ArithmeticImmediate: {
- switch (opcode->GetId()) {
+ switch (opcode->get().GetId()) {
case OpCode::Id::MOV32_IMM: {
regs.SetRegisterToFloat(instr.gpr0, 0, GetImmediate32(instr), 1, 1);
break;
@@ -1617,6 +1631,10 @@ private:
regs.GetRegisterAsFloat(instr.gpr8) + " * " +
GetImmediate32(instr),
1, 1, instr.fmul32.saturate, 0, true);
+ if (instr.op_32.generates_cc) {
+ LOG_CRITICAL(HW_GPU, "FMUL32 Generates an unhandled Control Code");
+ UNREACHABLE();
+ }
break;
}
case OpCode::Id::FADD32I: {
@@ -1640,6 +1658,10 @@ private:
}
regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " + " + op_b, 1, 1, false, 0, true);
+ if (instr.op_32.generates_cc) {
+ LOG_CRITICAL(HW_GPU, "FADD32 Generates an unhandled Control Code");
+ UNREACHABLE();
+ }
break;
}
}
@@ -1651,7 +1673,7 @@ private:
std::string op_a = instr.bfe.negate_a ? "-" : "";
op_a += regs.GetRegisterAsInteger(instr.gpr8);
- switch (opcode->GetId()) {
+ switch (opcode->get().GetId()) {
case OpCode::Id::BFE_IMM: {
std::string inner_shift =
'(' + op_a + " << " + std::to_string(instr.bfe.GetLeftShiftValue()) + ')';
@@ -1660,10 +1682,14 @@ private:
std::to_string(instr.bfe.GetLeftShiftValue() + instr.bfe.shift_position) + ')';
regs.SetRegisterToInteger(instr.gpr0, true, 0, outer_shift, 1, 1);
+ if (instr.generates_cc) {
+ LOG_CRITICAL(HW_GPU, "BFE Generates an unhandled Control Code");
+ UNREACHABLE();
+ }
break;
}
default: {
- LOG_CRITICAL(HW_GPU, "Unhandled BFE instruction: {}", opcode->GetName());
+ LOG_CRITICAL(HW_GPU, "Unhandled BFE instruction: {}", opcode->get().GetName());
UNREACHABLE();
}
}
@@ -1685,7 +1711,7 @@ private:
}
}
- switch (opcode->GetId()) {
+ switch (opcode->get().GetId()) {
case OpCode::Id::SHR_C:
case OpCode::Id::SHR_R:
case OpCode::Id::SHR_IMM: {
@@ -1697,15 +1723,23 @@ private:
// Cast to int is superfluous for arithmetic shift, it's only for a logical shift
regs.SetRegisterToInteger(instr.gpr0, true, 0, "int(" + op_a + " >> " + op_b + ')',
1, 1);
+ if (instr.generates_cc) {
+ LOG_CRITICAL(HW_GPU, "SHR Generates an unhandled Control Code");
+ UNREACHABLE();
+ }
break;
}
case OpCode::Id::SHL_C:
case OpCode::Id::SHL_R:
case OpCode::Id::SHL_IMM:
regs.SetRegisterToInteger(instr.gpr0, true, 0, op_a + " << " + op_b, 1, 1);
+ if (instr.generates_cc) {
+ LOG_CRITICAL(HW_GPU, "SHL Generates an unhandled Control Code");
+ UNREACHABLE();
+ }
break;
default: {
- LOG_CRITICAL(HW_GPU, "Unhandled shift instruction: {}", opcode->GetName());
+ LOG_CRITICAL(HW_GPU, "Unhandled shift instruction: {}", opcode->get().GetName());
UNREACHABLE();
}
}
@@ -1715,13 +1749,17 @@ private:
std::string op_a = regs.GetRegisterAsInteger(instr.gpr8);
std::string op_b = std::to_string(instr.alu.imm20_32.Value());
- switch (opcode->GetId()) {
+ switch (opcode->get().GetId()) {
case OpCode::Id::IADD32I:
if (instr.iadd32i.negate_a)
op_a = "-(" + op_a + ')';
regs.SetRegisterToInteger(instr.gpr0, true, 0, op_a + " + " + op_b, 1, 1,
instr.iadd32i.saturate != 0);
+ if (instr.op_32.generates_cc) {
+ LOG_CRITICAL(HW_GPU, "IADD32 Generates an unhandled Control Code");
+ UNREACHABLE();
+ }
break;
case OpCode::Id::LOP32I: {
if (instr.alu.lop32i.invert_a)
@@ -1733,11 +1771,15 @@ private:
WriteLogicOperation(instr.gpr0, instr.alu.lop32i.operation, op_a, op_b,
Tegra::Shader::PredicateResultMode::None,
Tegra::Shader::Pred::UnusedIndex);
+ if (instr.op_32.generates_cc) {
+ LOG_CRITICAL(HW_GPU, "LOP32I Generates an unhandled Control Code");
+ UNREACHABLE();
+ }
break;
}
default: {
LOG_CRITICAL(HW_GPU, "Unhandled ArithmeticIntegerImmediate instruction: {}",
- opcode->GetName());
+ opcode->get().GetName());
UNREACHABLE();
}
}
@@ -1757,7 +1799,7 @@ private:
}
}
- switch (opcode->GetId()) {
+ switch (opcode->get().GetId()) {
case OpCode::Id::IADD_C:
case OpCode::Id::IADD_R:
case OpCode::Id::IADD_IMM: {
@@ -1769,6 +1811,10 @@ private:
regs.SetRegisterToInteger(instr.gpr0, true, 0, op_a + " + " + op_b, 1, 1,
instr.alu.saturate_d);
+ if (instr.generates_cc) {
+ LOG_CRITICAL(HW_GPU, "IADD Generates an unhandled Control Code");
+ UNREACHABLE();
+ }
break;
}
case OpCode::Id::IADD3_C:
@@ -1793,7 +1839,7 @@ private:
}
};
- if (opcode->GetId() == OpCode::Id::IADD3_R) {
+ if (opcode->get().GetId() == OpCode::Id::IADD3_R) {
apply_height(instr.iadd3.height_a, op_a);
apply_height(instr.iadd3.height_b, op_b);
apply_height(instr.iadd3.height_c, op_c);
@@ -1809,7 +1855,7 @@ private:
op_c = "-(" + op_c + ')';
std::string result;
- if (opcode->GetId() == OpCode::Id::IADD3_R) {
+ if (opcode->get().GetId() == OpCode::Id::IADD3_R) {
switch (instr.iadd3.mode) {
case Tegra::Shader::IAdd3Mode::RightShift:
// TODO(tech4me): According to
@@ -1830,6 +1876,11 @@ private:
}
regs.SetRegisterToInteger(instr.gpr0, true, 0, result, 1, 1);
+
+ if (instr.generates_cc) {
+ LOG_CRITICAL(HW_GPU, "IADD3 Generates an unhandled Control Code");
+ UNREACHABLE();
+ }
break;
}
case OpCode::Id::ISCADD_C:
@@ -1845,6 +1896,10 @@ private:
regs.SetRegisterToInteger(instr.gpr0, true, 0,
"((" + op_a + " << " + shift + ") + " + op_b + ')', 1, 1);
+ if (instr.generates_cc) {
+ LOG_CRITICAL(HW_GPU, "ISCADD Generates an unhandled Control Code");
+ UNREACHABLE();
+ }
break;
}
case OpCode::Id::POPC_C:
@@ -1876,6 +1931,10 @@ private:
WriteLogicOperation(instr.gpr0, instr.alu.lop.operation, op_a, op_b,
instr.alu.lop.pred_result_mode, instr.alu.lop.pred48);
+ if (instr.generates_cc) {
+ LOG_CRITICAL(HW_GPU, "LOP Generates an unhandled Control Code");
+ UNREACHABLE();
+ }
break;
}
case OpCode::Id::LOP3_C:
@@ -1884,13 +1943,17 @@ private:
const std::string op_c = regs.GetRegisterAsInteger(instr.gpr39);
std::string lut;
- if (opcode->GetId() == OpCode::Id::LOP3_R) {
+ if (opcode->get().GetId() == OpCode::Id::LOP3_R) {
lut = '(' + std::to_string(instr.alu.lop3.GetImmLut28()) + ')';
} else {
lut = '(' + std::to_string(instr.alu.lop3.GetImmLut48()) + ')';
}
WriteLop3Instruction(instr.gpr0, op_a, op_b, op_c, lut);
+ if (instr.generates_cc) {
+ LOG_CRITICAL(HW_GPU, "LOP3 Generates an unhandled Control Code");
+ UNREACHABLE();
+ }
break;
}
case OpCode::Id::IMNMX_C:
@@ -1905,6 +1968,10 @@ private:
'(' + condition + ") ? min(" + parameters + ") : max(" +
parameters + ')',
1, 1);
+ if (instr.generates_cc) {
+ LOG_CRITICAL(HW_GPU, "IMNMX Generates an unhandled Control Code");
+ UNREACHABLE();
+ }
break;
}
case OpCode::Id::LEA_R2:
@@ -1914,7 +1981,7 @@ private:
case OpCode::Id::LEA_HI: {
std::string op_c;
- switch (opcode->GetId()) {
+ switch (opcode->get().GetId()) {
case OpCode::Id::LEA_R2: {
op_a = regs.GetRegisterAsInteger(instr.gpr20);
op_b = regs.GetRegisterAsInteger(instr.gpr39);
@@ -1959,7 +2026,8 @@ private:
op_b = regs.GetRegisterAsInteger(instr.gpr8);
op_a = std::to_string(instr.lea.imm.entry_a);
op_c = std::to_string(instr.lea.imm.entry_b);
- LOG_CRITICAL(HW_GPU, "Unhandled LEA subinstruction: {}", opcode->GetName());
+ LOG_CRITICAL(HW_GPU, "Unhandled LEA subinstruction: {}",
+ opcode->get().GetName());
UNREACHABLE();
}
}
@@ -1974,7 +2042,7 @@ private:
}
default: {
LOG_CRITICAL(HW_GPU, "Unhandled ArithmeticInteger instruction: {}",
- opcode->GetName());
+ opcode->get().GetName());
UNREACHABLE();
}
}
@@ -1982,20 +2050,21 @@ private:
break;
}
case OpCode::Type::ArithmeticHalf: {
- if (opcode->GetId() == OpCode::Id::HADD2_C || opcode->GetId() == OpCode::Id::HADD2_R) {
+ if (opcode->get().GetId() == OpCode::Id::HADD2_C ||
+ opcode->get().GetId() == OpCode::Id::HADD2_R) {
ASSERT_MSG(instr.alu_half.ftz == 0, "Unimplemented");
}
const bool negate_a =
- opcode->GetId() != OpCode::Id::HMUL2_R && instr.alu_half.negate_a != 0;
+ opcode->get().GetId() != OpCode::Id::HMUL2_R && instr.alu_half.negate_a != 0;
const bool negate_b =
- opcode->GetId() != OpCode::Id::HMUL2_C && instr.alu_half.negate_b != 0;
+ opcode->get().GetId() != OpCode::Id::HMUL2_C && instr.alu_half.negate_b != 0;
const std::string op_a =
GetHalfFloat(regs.GetRegisterAsInteger(instr.gpr8, 0, false), instr.alu_half.type_a,
instr.alu_half.abs_a != 0, negate_a);
std::string op_b;
- switch (opcode->GetId()) {
+ switch (opcode->get().GetId()) {
case OpCode::Id::HADD2_C:
case OpCode::Id::HMUL2_C:
op_b = regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset,
@@ -2013,7 +2082,7 @@ private:
op_b = GetHalfFloat(op_b, instr.alu_half.type_b, instr.alu_half.abs_b != 0, negate_b);
const std::string result = [&]() {
- switch (opcode->GetId()) {
+ switch (opcode->get().GetId()) {
case OpCode::Id::HADD2_C:
case OpCode::Id::HADD2_R:
return '(' + op_a + " + " + op_b + ')';
@@ -2021,7 +2090,8 @@ private:
case OpCode::Id::HMUL2_R:
return '(' + op_a + " * " + op_b + ')';
default:
- LOG_CRITICAL(HW_GPU, "Unhandled half float instruction: {}", opcode->GetName());
+ LOG_CRITICAL(HW_GPU, "Unhandled half float instruction: {}",
+ opcode->get().GetName());
UNREACHABLE();
return std::string("0");
}
@@ -2032,7 +2102,7 @@ private:
break;
}
case OpCode::Type::ArithmeticHalfImmediate: {
- if (opcode->GetId() == OpCode::Id::HADD2_IMM) {
+ if (opcode->get().GetId() == OpCode::Id::HADD2_IMM) {
ASSERT_MSG(instr.alu_half_imm.ftz == 0, "Unimplemented");
} else {
ASSERT_MSG(instr.alu_half_imm.precision == Tegra::Shader::HalfPrecision::None,
@@ -2046,7 +2116,7 @@ private:
const std::string op_b = UnpackHalfImmediate(instr, true);
const std::string result = [&]() {
- switch (opcode->GetId()) {
+ switch (opcode->get().GetId()) {
case OpCode::Id::HADD2_IMM:
return op_a + " + " + op_b;
case OpCode::Id::HMUL2_IMM:
@@ -2072,7 +2142,7 @@ private:
ASSERT_MSG(instr.ffma.tab5980_1 == 0, "FFMA tab5980_1({}) not implemented",
instr.ffma.tab5980_1.Value());
- switch (opcode->GetId()) {
+ switch (opcode->get().GetId()) {
case OpCode::Id::FFMA_CR: {
op_b += regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset,
GLSLRegister::Type::Float);
@@ -2096,25 +2166,29 @@ private:
break;
}
default: {
- LOG_CRITICAL(HW_GPU, "Unhandled FFMA instruction: {}", opcode->GetName());
+ LOG_CRITICAL(HW_GPU, "Unhandled FFMA instruction: {}", opcode->get().GetName());
UNREACHABLE();
}
}
regs.SetRegisterToFloat(instr.gpr0, 0, "fma(" + op_a + ", " + op_b + ", " + op_c + ')',
1, 1, instr.alu.saturate_d, 0, true);
+ if (instr.generates_cc) {
+ LOG_CRITICAL(HW_GPU, "FFMA Generates an unhandled Control Code");
+ UNREACHABLE();
+ }
break;
}
case OpCode::Type::Hfma2: {
- if (opcode->GetId() == OpCode::Id::HFMA2_RR) {
+ if (opcode->get().GetId() == OpCode::Id::HFMA2_RR) {
ASSERT_MSG(instr.hfma2.rr.precision == Tegra::Shader::HalfPrecision::None,
"Unimplemented");
} else {
ASSERT_MSG(instr.hfma2.precision == Tegra::Shader::HalfPrecision::None,
"Unimplemented");
}
- const bool saturate = opcode->GetId() == OpCode::Id::HFMA2_RR
+ const bool saturate = opcode->get().GetId() == OpCode::Id::HFMA2_RR
? instr.hfma2.rr.saturate != 0
: instr.hfma2.saturate != 0;
@@ -2122,7 +2196,7 @@ private:
GetHalfFloat(regs.GetRegisterAsInteger(instr.gpr8, 0, false), instr.hfma2.type_a);
std::string op_b, op_c;
- switch (opcode->GetId()) {
+ switch (opcode->get().GetId()) {
case OpCode::Id::HFMA2_CR:
op_b = GetHalfFloat(regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset,
GLSLRegister::Type::UnsignedInteger),
@@ -2160,7 +2234,7 @@ private:
break;
}
case OpCode::Type::Conversion: {
- switch (opcode->GetId()) {
+ switch (opcode->get().GetId()) {
case OpCode::Id::I2I_R: {
ASSERT_MSG(!instr.conversion.selector, "Unimplemented");
@@ -2208,6 +2282,11 @@ private:
}
regs.SetRegisterToFloat(instr.gpr0, 0, op_a, 1, 1);
+
+ if (instr.generates_cc) {
+ LOG_CRITICAL(HW_GPU, "I2F Generates an unhandled Control Code");
+ UNREACHABLE();
+ }
break;
}
case OpCode::Id::F2F_R: {
@@ -2246,6 +2325,11 @@ private:
}
regs.SetRegisterToFloat(instr.gpr0, 0, op_a, 1, 1, instr.alu.saturate_d);
+
+ if (instr.generates_cc) {
+ LOG_CRITICAL(HW_GPU, "F2F Generates an unhandled Control Code");
+ UNREACHABLE();
+ }
break;
}
case OpCode::Id::F2I_R:
@@ -2295,17 +2379,22 @@ private:
regs.SetRegisterToInteger(instr.gpr0, instr.conversion.is_output_signed, 0, op_a, 1,
1, false, 0, instr.conversion.dest_size);
+ if (instr.generates_cc) {
+ LOG_CRITICAL(HW_GPU, "F2I Generates an unhandled Control Code");
+ UNREACHABLE();
+ }
break;
}
default: {
- LOG_CRITICAL(HW_GPU, "Unhandled conversion instruction: {}", opcode->GetName());
+ LOG_CRITICAL(HW_GPU, "Unhandled conversion instruction: {}",
+ opcode->get().GetName());
UNREACHABLE();
}
}
break;
}
case OpCode::Type::Memory: {
- switch (opcode->GetId()) {
+ switch (opcode->get().GetId()) {
case OpCode::Id::LD_A: {
// Note: Shouldn't this be interp mode flat? As in no interpolation made.
ASSERT_MSG(instr.gpr8.Value() == Register::ZeroIndex,
@@ -2949,7 +3038,7 @@ private:
break;
}
default: {
- LOG_CRITICAL(HW_GPU, "Unhandled memory instruction: {}", opcode->GetName());
+ LOG_CRITICAL(HW_GPU, "Unhandled memory instruction: {}", opcode->get().GetName());
UNREACHABLE();
}
}
@@ -3043,7 +3132,7 @@ private:
instr.hsetp2.abs_a, instr.hsetp2.negate_a);
const std::string op_b = [&]() {
- switch (opcode->GetId()) {
+ switch (opcode->get().GetId()) {
case OpCode::Id::HSETP2_R:
return GetHalfFloat(regs.GetRegisterAsInteger(instr.gpr20, 0, false),
instr.hsetp2.type_b, instr.hsetp2.abs_a,
@@ -3102,10 +3191,15 @@ private:
regs.SetRegisterToFloat(instr.gpr0, 0, value, 1, 1);
}
+ if (instr.generates_cc) {
+ LOG_CRITICAL(HW_GPU, "PSET Generates an unhandled Control Code");
+ UNREACHABLE();
+ }
+
break;
}
case OpCode::Type::PredicateSetPredicate: {
- switch (opcode->GetId()) {
+ switch (opcode->get().GetId()) {
case OpCode::Id::PSETP: {
const std::string op_a =
GetPredicateCondition(instr.psetp.pred12, instr.psetp.neg_pred12 != 0);
@@ -3151,7 +3245,8 @@ private:
break;
}
default: {
- LOG_CRITICAL(HW_GPU, "Unhandled predicate instruction: {}", opcode->GetName());
+ LOG_CRITICAL(HW_GPU, "Unhandled predicate instruction: {}",
+ opcode->get().GetName());
UNREACHABLE();
}
}
@@ -3239,7 +3334,7 @@ private:
instr.hset2.abs_a != 0, instr.hset2.negate_a != 0);
const std::string op_b = [&]() {
- switch (opcode->GetId()) {
+ switch (opcode->get().GetId()) {
case OpCode::Id::HSET2_R:
return GetHalfFloat(regs.GetRegisterAsInteger(instr.gpr20, 0, false),
instr.hset2.type_b, instr.hset2.abs_b != 0,
@@ -3288,7 +3383,7 @@ private:
const bool is_signed{instr.xmad.sign_a == 1};
bool is_merge{};
- switch (opcode->GetId()) {
+ switch (opcode->get().GetId()) {
case OpCode::Id::XMAD_CR: {
is_merge = instr.xmad.merge_56;
op_b += regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset,
@@ -3317,7 +3412,7 @@ private:
break;
}
default: {
- LOG_CRITICAL(HW_GPU, "Unhandled XMAD instruction: {}", opcode->GetName());
+ LOG_CRITICAL(HW_GPU, "Unhandled XMAD instruction: {}", opcode->get().GetName());
UNREACHABLE();
}
}
@@ -3366,15 +3461,25 @@ private:
}
regs.SetRegisterToInteger(instr.gpr0, is_signed, 0, sum, 1, 1);
+ if (instr.generates_cc) {
+ LOG_CRITICAL(HW_GPU, "XMAD Generates an unhandled Control Code");
+ UNREACHABLE();
+ }
break;
}
default: {
- switch (opcode->GetId()) {
+ switch (opcode->get().GetId()) {
case OpCode::Id::EXIT: {
if (stage == Maxwell3D::Regs::ShaderStage::Fragment) {
EmitFragmentOutputsWrite();
}
+ const Tegra::Shader::ControlCode cc = instr.flow_control_code;
+ if (cc != Tegra::Shader::ControlCode::T) {
+ LOG_CRITICAL(HW_GPU, "EXIT Control Code used: {}", static_cast<u32>(cc));
+ UNREACHABLE();
+ }
+
switch (instr.flow.cond) {
case Tegra::Shader::FlowCondition::Always:
shader.AddLine("return true;");
@@ -3404,6 +3509,11 @@ private:
// Enclose "discard" in a conditional, so that GLSL compilation does not complain
// about unexecuted instructions that may follow this.
+ const Tegra::Shader::ControlCode cc = instr.flow_control_code;
+ if (cc != Tegra::Shader::ControlCode::T) {
+ LOG_CRITICAL(HW_GPU, "KIL Control Code used: {}", static_cast<u32>(cc));
+ UNREACHABLE();
+ }
shader.AddLine("if (true) {");
++shader.scope;
shader.AddLine("discard;");
@@ -3461,6 +3571,11 @@ private:
case OpCode::Id::BRA: {
ASSERT_MSG(instr.bra.constant_buffer == 0,
"BRA with constant buffers are not implemented");
+ const Tegra::Shader::ControlCode cc = instr.flow_control_code;
+ if (cc != Tegra::Shader::ControlCode::T) {
+ LOG_CRITICAL(HW_GPU, "BRA Control Code used: {}", static_cast<u32>(cc));
+ UNREACHABLE();
+ }
const u32 target = offset + instr.bra.GetBranchTarget();
shader.AddLine("{ jmp_to = " + std::to_string(target) + "u; break; }");
break;
@@ -3501,13 +3616,21 @@ private:
}
case OpCode::Id::SYNC: {
// The SYNC opcode jumps to the address previously set by the SSY opcode
- ASSERT(instr.flow.cond == Tegra::Shader::FlowCondition::Always);
+ const Tegra::Shader::ControlCode cc = instr.flow_control_code;
+ if (cc != Tegra::Shader::ControlCode::T) {
+ LOG_CRITICAL(HW_GPU, "SYNC Control Code used: {}", static_cast<u32>(cc));
+ UNREACHABLE();
+ }
EmitPopFromFlowStack();
break;
}
case OpCode::Id::BRK: {
// The BRK opcode jumps to the address previously set by the PBK opcode
- ASSERT(instr.flow.cond == Tegra::Shader::FlowCondition::Always);
+ const Tegra::Shader::ControlCode cc = instr.flow_control_code;
+ if (cc != Tegra::Shader::ControlCode::T) {
+ LOG_CRITICAL(HW_GPU, "BRK Control Code used: {}", static_cast<u32>(cc));
+ UNREACHABLE();
+ }
EmitPopFromFlowStack();
break;
}
@@ -3537,6 +3660,11 @@ private:
regs.SetRegisterToInteger(instr.gpr0, result_signed, 1, result, 1, 1,
instr.vmad.saturate == 1, 0, Register::Size::Word,
instr.vmad.cc);
+ if (instr.generates_cc) {
+ LOG_CRITICAL(HW_GPU, "VMAD Generates an unhandled Control Code");
+ UNREACHABLE();
+ }
+
break;
}
case OpCode::Id::VSETP: {
@@ -3564,7 +3692,7 @@ private:
break;
}
default: {
- LOG_CRITICAL(HW_GPU, "Unhandled instruction: {}", opcode->GetName());
+ LOG_CRITICAL(HW_GPU, "Unhandled instruction: {}", opcode->get().GetName());
UNREACHABLE();
}
}
@@ -3705,9 +3833,9 @@ std::string GetCommonDeclarations() {
RasterizerOpenGL::MaxConstbufferSize / sizeof(GLvec4));
}
-boost::optional<ProgramResult> DecompileProgram(const ProgramCode& program_code, u32 main_offset,
- Maxwell3D::Regs::ShaderStage stage,
- const std::string& suffix) {
+std::optional<ProgramResult> DecompileProgram(const ProgramCode& program_code, u32 main_offset,
+ Maxwell3D::Regs::ShaderStage stage,
+ const std::string& suffix) {
try {
const auto subroutines =
ControlFlowAnalyzer(program_code, main_offset, suffix).GetSubroutines();
@@ -3716,7 +3844,7 @@ boost::optional<ProgramResult> DecompileProgram(const ProgramCode& program_code,
} catch (const DecompileFail& exception) {
LOG_ERROR(HW_GPU, "Shader decompilation failed: {}", exception.what());
}
- return boost::none;
+ return {};
}
} // namespace OpenGL::GLShader::Decompiler
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-21 11:26:35 +0200