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-rw-r--r--src/video_core/engines/maxwell_3d.h81
-rw-r--r--src/video_core/engines/shader_bytecode.h71
-rw-r--r--src/video_core/engines/shader_header.h55
3 files changed, 169 insertions, 38 deletions
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index d24c9f657..5cf6a4cc3 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -303,6 +303,10 @@ public:
return (type == Type::SignedNorm) || (type == Type::UnsignedNorm);
}
+ bool IsConstant() const {
+ return constant;
+ }
+
bool IsValid() const {
return size != Size::Invalid;
}
@@ -312,6 +316,35 @@ public:
}
};
+ struct MsaaSampleLocation {
+ union {
+ BitField<0, 4, u32> x0;
+ BitField<4, 4, u32> y0;
+ BitField<8, 4, u32> x1;
+ BitField<12, 4, u32> y1;
+ BitField<16, 4, u32> x2;
+ BitField<20, 4, u32> y2;
+ BitField<24, 4, u32> x3;
+ BitField<28, 4, u32> y3;
+ };
+
+ constexpr std::pair<u32, u32> Location(int index) const {
+ switch (index) {
+ case 0:
+ return {x0, y0};
+ case 1:
+ return {x1, y1};
+ case 2:
+ return {x2, y2};
+ case 3:
+ return {x3, y3};
+ default:
+ UNREACHABLE();
+ return {0, 0};
+ }
+ }
+ };
+
enum class DepthMode : u32 {
MinusOneToOne = 0,
ZeroToOne = 1,
@@ -793,7 +826,13 @@ public:
u32 rt_separate_frag_data;
- INSERT_UNION_PADDING_WORDS(0xC);
+ INSERT_UNION_PADDING_WORDS(0x1);
+
+ u32 multisample_raster_enable;
+ u32 multisample_raster_samples;
+ std::array<u32, 4> multisample_sample_mask;
+
+ INSERT_UNION_PADDING_WORDS(0x5);
struct {
u32 address_high;
@@ -830,7 +869,16 @@ public:
std::array<VertexAttribute, NumVertexAttributes> vertex_attrib_format;
- INSERT_UNION_PADDING_WORDS(0xF);
+ std::array<MsaaSampleLocation, 4> multisample_sample_locations;
+
+ INSERT_UNION_PADDING_WORDS(0x2);
+
+ union {
+ BitField<0, 1, u32> enable;
+ BitField<4, 3, u32> target;
+ } multisample_coverage_to_color;
+
+ INSERT_UNION_PADDING_WORDS(0x8);
struct {
union {
@@ -922,7 +970,10 @@ public:
BitField<4, 1, u32> triangle_rast_flip;
} screen_y_control;
- INSERT_UNION_PADDING_WORDS(0x21);
+ float line_width_smooth;
+ float line_width_aliased;
+
+ INSERT_UNION_PADDING_WORDS(0x1F);
u32 vb_element_base;
u32 vb_base_instance;
@@ -943,7 +994,7 @@ public:
CounterReset counter_reset;
- INSERT_UNION_PADDING_WORDS(0x1);
+ u32 multisample_enable;
u32 zeta_enable;
@@ -980,7 +1031,7 @@ public:
float polygon_offset_factor;
- INSERT_UNION_PADDING_WORDS(0x1);
+ u32 line_smooth_enable;
struct {
u32 tic_address_high;
@@ -1007,7 +1058,11 @@ public:
float polygon_offset_units;
- INSERT_UNION_PADDING_WORDS(0x11);
+ INSERT_UNION_PADDING_WORDS(0x4);
+
+ Tegra::Texture::MsaaMode multisample_mode;
+
+ INSERT_UNION_PADDING_WORDS(0xC);
union {
BitField<2, 1, u32> coord_origin;
@@ -1507,12 +1562,17 @@ ASSERT_REG_POSITION(stencil_back_func_ref, 0x3D5);
ASSERT_REG_POSITION(stencil_back_mask, 0x3D6);
ASSERT_REG_POSITION(stencil_back_func_mask, 0x3D7);
ASSERT_REG_POSITION(color_mask_common, 0x3E4);
-ASSERT_REG_POSITION(rt_separate_frag_data, 0x3EB);
ASSERT_REG_POSITION(depth_bounds, 0x3E7);
+ASSERT_REG_POSITION(rt_separate_frag_data, 0x3EB);
+ASSERT_REG_POSITION(multisample_raster_enable, 0x3ED);
+ASSERT_REG_POSITION(multisample_raster_samples, 0x3EE);
+ASSERT_REG_POSITION(multisample_sample_mask, 0x3EF);
ASSERT_REG_POSITION(zeta, 0x3F8);
ASSERT_REG_POSITION(clear_flags, 0x43E);
ASSERT_REG_POSITION(fill_rectangle, 0x44F);
ASSERT_REG_POSITION(vertex_attrib_format, 0x458);
+ASSERT_REG_POSITION(multisample_sample_locations, 0x478);
+ASSERT_REG_POSITION(multisample_coverage_to_color, 0x47E);
ASSERT_REG_POSITION(rt_control, 0x487);
ASSERT_REG_POSITION(zeta_width, 0x48a);
ASSERT_REG_POSITION(zeta_height, 0x48b);
@@ -1538,6 +1598,8 @@ ASSERT_REG_POSITION(stencil_front_func_mask, 0x4E6);
ASSERT_REG_POSITION(stencil_front_mask, 0x4E7);
ASSERT_REG_POSITION(frag_color_clamp, 0x4EA);
ASSERT_REG_POSITION(screen_y_control, 0x4EB);
+ASSERT_REG_POSITION(line_width_smooth, 0x4EC);
+ASSERT_REG_POSITION(line_width_aliased, 0x4ED);
ASSERT_REG_POSITION(vb_element_base, 0x50D);
ASSERT_REG_POSITION(vb_base_instance, 0x50E);
ASSERT_REG_POSITION(clip_distance_enabled, 0x544);
@@ -1545,11 +1607,13 @@ ASSERT_REG_POSITION(samplecnt_enable, 0x545);
ASSERT_REG_POSITION(point_size, 0x546);
ASSERT_REG_POSITION(point_sprite_enable, 0x548);
ASSERT_REG_POSITION(counter_reset, 0x54C);
+ASSERT_REG_POSITION(multisample_enable, 0x54D);
ASSERT_REG_POSITION(zeta_enable, 0x54E);
ASSERT_REG_POSITION(multisample_control, 0x54F);
ASSERT_REG_POSITION(condition, 0x554);
ASSERT_REG_POSITION(tsc, 0x557);
-ASSERT_REG_POSITION(polygon_offset_factor, 0x55b);
+ASSERT_REG_POSITION(polygon_offset_factor, 0x55B);
+ASSERT_REG_POSITION(line_smooth_enable, 0x55C);
ASSERT_REG_POSITION(tic, 0x55D);
ASSERT_REG_POSITION(stencil_two_side_enable, 0x565);
ASSERT_REG_POSITION(stencil_back_op_fail, 0x566);
@@ -1558,6 +1622,7 @@ ASSERT_REG_POSITION(stencil_back_op_zpass, 0x568);
ASSERT_REG_POSITION(stencil_back_func_func, 0x569);
ASSERT_REG_POSITION(framebuffer_srgb, 0x56E);
ASSERT_REG_POSITION(polygon_offset_units, 0x56F);
+ASSERT_REG_POSITION(multisample_mode, 0x574);
ASSERT_REG_POSITION(point_coord_replace, 0x581);
ASSERT_REG_POSITION(code_address, 0x582);
ASSERT_REG_POSITION(draw, 0x585);
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index a31947ef3..5e9cfba22 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -290,6 +290,23 @@ enum class VmadShr : u64 {
Shr15 = 2,
};
+enum class VmnmxType : u64 {
+ Bits8,
+ Bits16,
+ Bits32,
+};
+
+enum class VmnmxOperation : u64 {
+ Mrg_16H = 0,
+ Mrg_16L = 1,
+ Mrg_8B0 = 2,
+ Mrg_8B2 = 3,
+ Acc = 4,
+ Min = 5,
+ Max = 6,
+ Nop = 7,
+};
+
enum class XmadMode : u64 {
None = 0,
CLo = 1,
@@ -1657,6 +1674,42 @@ union Instruction {
} vmad;
union {
+ BitField<54, 1, u64> is_dest_signed;
+ BitField<48, 1, u64> is_src_a_signed;
+ BitField<49, 1, u64> is_src_b_signed;
+ BitField<37, 2, u64> src_format_a;
+ BitField<29, 2, u64> src_format_b;
+ BitField<56, 1, u64> mx;
+ BitField<55, 1, u64> sat;
+ BitField<36, 2, u64> selector_a;
+ BitField<28, 2, u64> selector_b;
+ BitField<50, 1, u64> is_op_b_register;
+ BitField<51, 3, VmnmxOperation> operation;
+
+ VmnmxType SourceFormatA() const {
+ switch (src_format_a) {
+ case 0b11:
+ return VmnmxType::Bits32;
+ case 0b10:
+ return VmnmxType::Bits16;
+ default:
+ return VmnmxType::Bits8;
+ }
+ }
+
+ VmnmxType SourceFormatB() const {
+ switch (src_format_b) {
+ case 0b11:
+ return VmnmxType::Bits32;
+ case 0b10:
+ return VmnmxType::Bits16;
+ default:
+ return VmnmxType::Bits8;
+ }
+ }
+ } vmnmx;
+
+ union {
BitField<20, 16, u64> imm20_16;
BitField<35, 1, u64> high_b_rr; // used on RR
BitField<36, 1, u64> product_shift_left;
@@ -1718,6 +1771,7 @@ public:
BRK,
DEPBAR,
VOTE,
+ VOTE_VTG,
SHFL,
FSWZADD,
BFE_C,
@@ -1765,9 +1819,11 @@ public:
IPA,
OUT_R, // Emit vertex/primitive
ISBERD,
+ BAR,
MEMBAR,
VMAD,
VSETP,
+ VMNMX,
FFMA_IMM, // Fused Multiply and Add
FFMA_CR,
FFMA_RC,
@@ -1822,7 +1878,8 @@ public:
ICMP_R,
ICMP_CR,
ICMP_IMM,
- FCMP_R,
+ FCMP_RR,
+ FCMP_RC,
MUFU, // Multi-Function Operator
RRO_C, // Range Reduction Operator
RRO_R,
@@ -1849,7 +1906,7 @@ public:
MOV_C,
MOV_R,
MOV_IMM,
- MOV_SYS,
+ S2R,
MOV32_IMM,
SHL_C,
SHL_R,
@@ -2033,6 +2090,7 @@ private:
INST("111000110000----", Id::EXIT, Type::Flow, "EXIT"),
INST("1111000011110---", Id::DEPBAR, Type::Synch, "DEPBAR"),
INST("0101000011011---", Id::VOTE, Type::Warp, "VOTE"),
+ INST("0101000011100---", Id::VOTE_VTG, Type::Warp, "VOTE_VTG"),
INST("1110111100010---", Id::SHFL, Type::Warp, "SHFL"),
INST("0101000011111---", Id::FSWZADD, Type::Warp, "FSWZADD"),
INST("1110111111011---", Id::LD_A, Type::Memory, "LD_A"),
@@ -2071,9 +2129,11 @@ private:
INST("11100000--------", Id::IPA, Type::Trivial, "IPA"),
INST("1111101111100---", Id::OUT_R, Type::Trivial, "OUT_R"),
INST("1110111111010---", Id::ISBERD, Type::Trivial, "ISBERD"),
+ INST("1111000010101---", Id::BAR, Type::Trivial, "BAR"),
INST("1110111110011---", Id::MEMBAR, Type::Trivial, "MEMBAR"),
INST("01011111--------", Id::VMAD, Type::Video, "VMAD"),
INST("0101000011110---", Id::VSETP, Type::Video, "VSETP"),
+ INST("0011101---------", Id::VMNMX, Type::Video, "VMNMX"),
INST("0011001-1-------", Id::FFMA_IMM, Type::Ffma, "FFMA_IMM"),
INST("010010011-------", Id::FFMA_CR, Type::Ffma, "FFMA_CR"),
INST("010100011-------", Id::FFMA_RC, Type::Ffma, "FFMA_RC"),
@@ -2128,7 +2188,8 @@ private:
INST("0101110100100---", Id::HSETP2_R, Type::HalfSetPredicate, "HSETP2_R"),
INST("0111111-0-------", Id::HSETP2_IMM, Type::HalfSetPredicate, "HSETP2_IMM"),
INST("0101110100011---", Id::HSET2_R, Type::HalfSet, "HSET2_R"),
- INST("010110111010----", Id::FCMP_R, Type::Arithmetic, "FCMP_R"),
+ INST("010110111010----", Id::FCMP_RR, Type::Arithmetic, "FCMP_RR"),
+ INST("010010111010----", Id::FCMP_RC, Type::Arithmetic, "FCMP_RC"),
INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"),
INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"),
@@ -2142,7 +2203,7 @@ private:
INST("0100110010011---", Id::MOV_C, Type::Arithmetic, "MOV_C"),
INST("0101110010011---", Id::MOV_R, Type::Arithmetic, "MOV_R"),
INST("0011100-10011---", Id::MOV_IMM, Type::Arithmetic, "MOV_IMM"),
- INST("1111000011001---", Id::MOV_SYS, Type::Trivial, "MOV_SYS"),
+ INST("1111000011001---", Id::S2R, Type::Trivial, "S2R"),
INST("000000010000----", Id::MOV32_IMM, Type::ArithmeticImmediate, "MOV32_IMM"),
INST("0100110001100---", Id::FMNMX_C, Type::Arithmetic, "FMNMX_C"),
INST("0101110001100---", Id::FMNMX_R, Type::Arithmetic, "FMNMX_R"),
@@ -2174,7 +2235,7 @@ private:
INST("0011011-11111---", Id::SHF_LEFT_IMM, Type::Shift, "SHF_LEFT_IMM"),
INST("0100110011100---", Id::I2I_C, Type::Conversion, "I2I_C"),
INST("0101110011100---", Id::I2I_R, Type::Conversion, "I2I_R"),
- INST("0011101-11100---", Id::I2I_IMM, Type::Conversion, "I2I_IMM"),
+ INST("0011100-11100---", Id::I2I_IMM, Type::Conversion, "I2I_IMM"),
INST("0100110010111---", Id::I2F_C, Type::Conversion, "I2F_C"),
INST("0101110010111---", Id::I2F_R, Type::Conversion, "I2F_R"),
INST("0011100-10111---", Id::I2F_IMM, Type::Conversion, "I2F_IMM"),
diff --git a/src/video_core/engines/shader_header.h b/src/video_core/engines/shader_header.h
index bc80661d8..72e2a33d5 100644
--- a/src/video_core/engines/shader_header.h
+++ b/src/video_core/engines/shader_header.h
@@ -4,6 +4,9 @@
#pragma once
+#include <array>
+#include <optional>
+
#include "common/bit_field.h"
#include "common/common_funcs.h"
#include "common/common_types.h"
@@ -16,7 +19,7 @@ enum class OutputTopology : u32 {
TriangleStrip = 7,
};
-enum class AttributeUse : u8 {
+enum class PixelImap : u8 {
Unused = 0,
Constant = 1,
Perspective = 2,
@@ -24,7 +27,7 @@ enum class AttributeUse : u8 {
};
// Documentation in:
-// http://download.nvidia.com/open-gpu-doc/Shader-Program-Header/1/Shader-Program-Header.html#ImapTexture
+// http://download.nvidia.com/open-gpu-doc/Shader-Program-Header/1/Shader-Program-Header.html
struct Header {
union {
BitField<0, 5, u32> sph_type;
@@ -59,8 +62,8 @@ struct Header {
union {
BitField<0, 12, u32> max_output_vertices;
BitField<12, 8, u32> store_req_start; // NOTE: not used by geometry shaders.
- BitField<24, 4, u32> reserved;
- BitField<12, 8, u32> store_req_end; // NOTE: not used by geometry shaders.
+ BitField<20, 4, u32> reserved;
+ BitField<24, 8, u32> store_req_end; // NOTE: not used by geometry shaders.
} common4{};
union {
@@ -93,17 +96,20 @@ struct Header {
struct {
INSERT_UNION_PADDING_BYTES(3); // ImapSystemValuesA
INSERT_UNION_PADDING_BYTES(1); // ImapSystemValuesB
+
union {
- BitField<0, 2, AttributeUse> x;
- BitField<2, 2, AttributeUse> y;
- BitField<4, 2, AttributeUse> w;
- BitField<6, 2, AttributeUse> z;
+ BitField<0, 2, PixelImap> x;
+ BitField<2, 2, PixelImap> y;
+ BitField<4, 2, PixelImap> z;
+ BitField<6, 2, PixelImap> w;
u8 raw;
} imap_generic_vector[32];
+
INSERT_UNION_PADDING_BYTES(2); // ImapColor
INSERT_UNION_PADDING_BYTES(2); // ImapSystemValuesC
INSERT_UNION_PADDING_BYTES(10); // ImapFixedFncTexture[10]
INSERT_UNION_PADDING_BYTES(2); // ImapReserved
+
struct {
u32 target;
union {
@@ -112,31 +118,30 @@ struct Header {
BitField<2, 30, u32> reserved;
};
} omap;
+
bool IsColorComponentOutputEnabled(u32 render_target, u32 component) const {
const u32 bit = render_target * 4 + component;
return omap.target & (1 << bit);
}
- AttributeUse GetAttributeIndexUse(u32 attribute, u32 index) const {
- return static_cast<AttributeUse>(
- (imap_generic_vector[attribute].raw >> (index * 2)) & 0x03);
- }
- AttributeUse GetAttributeUse(u32 attribute) const {
- AttributeUse result = AttributeUse::Unused;
- for (u32 i = 0; i < 4; i++) {
- const auto index = GetAttributeIndexUse(attribute, i);
- if (index == AttributeUse::Unused) {
- continue;
- }
- if (result == AttributeUse::Unused || result == index) {
- result = index;
+
+ PixelImap GetPixelImap(u32 attribute) const {
+ const auto get_index = [this, attribute](u32 index) {
+ return static_cast<PixelImap>(
+ (imap_generic_vector[attribute].raw >> (index * 2)) & 3);
+ };
+
+ std::optional<PixelImap> result;
+ for (u32 component = 0; component < 4; ++component) {
+ const PixelImap index = get_index(component);
+ if (index == PixelImap::Unused) {
continue;
}
- LOG_CRITICAL(HW_GPU, "Generic Attribute Conflict in Interpolation Mode");
- if (index == AttributeUse::Perspective) {
- result = index;
+ if (result && result != index) {
+ LOG_CRITICAL(HW_GPU, "Generic attribute conflict in interpolation mode");
}
+ result = index;
}
- return result;
+ return result.value_or(PixelImap::Unused);
}
} ps;
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-19 14:12:37 +0200