2 files changed, 15 insertions, 5 deletions
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index eff6abd55..4f137e693 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -631,7 +631,16 @@ public:
                     }
                 } zeta;
 
-                INSERT_PADDING_WORDS(0x5B);
+                INSERT_PADDING_WORDS(0x41);
+
+                union {
+                    BitField<0, 4, u32> stencil;
+                    BitField<4, 4, u32> unknown;
+                    BitField<8, 4, u32> scissor;
+                    BitField<12, 4, u32> viewport;
+                } clear_flags;
+
+                INSERT_PADDING_WORDS(0x19);
 
                 std::array<VertexAttribute, NumVertexAttributes> vertex_attrib_format;
 
@@ -1134,6 +1143,7 @@ ASSERT_REG_POSITION(stencil_back_func_mask, 0x3D7);
 ASSERT_REG_POSITION(color_mask_common, 0x3E4);
 ASSERT_REG_POSITION(rt_separate_frag_data, 0x3EB);
 ASSERT_REG_POSITION(zeta, 0x3F8);
+ASSERT_REG_POSITION(clear_flags, 0x43E);
 ASSERT_REG_POSITION(vertex_attrib_format, 0x458);
 ASSERT_REG_POSITION(rt_control, 0x487);
 ASSERT_REG_POSITION(zeta_width, 0x48a);
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index c0275afb5..639bedb80 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -155,6 +155,7 @@ enum class PredCondition : u64 {
     NotEqual = 5,
     GreaterEqual = 6,
     LessThanWithNan = 9,
+    LessEqualWithNan = 11,
     GreaterThanWithNan = 12,
     NotEqualWithNan = 13,
     GreaterEqualWithNan = 14,
@@ -263,7 +264,7 @@ enum class FlowCondition : u64 {
     Fcsm_Tr = 0x1C, // TODO(bunnei): What is this used for?
 };
 
-enum class ControlCode : u64 {
+enum class ConditionCode : u64 {
     F = 0,
     LT = 1,
     EQ = 2,
@@ -571,7 +572,6 @@ union Instruction {
         BitField<39, 2, u64> tab5cb8_2;
         BitField<41, 3, u64> tab5c68_1;
         BitField<44, 2, u64> tab5c68_0;
-        BitField<47, 1, u64> cc;
         BitField<48, 1, u64> negate_b;
     } fmul;
 
@@ -833,7 +833,7 @@ union Instruction {
     union {
         BitField<0, 3, u64> pred0;
         BitField<3, 3, u64> pred3;
-        BitField<8, 5, ControlCode> cc; // flag in cc
+        BitField<8, 5, ConditionCode> cc; // flag in cc
         BitField<39, 3, u64> pred39;
         BitField<42, 1, u64> neg_pred39;
         BitField<45, 4, PredOperation> op; // op with pred39
@@ -1237,7 +1237,7 @@ union Instruction {
     BitField<60, 1, u64> is_b_gpr;
     BitField<59, 1, u64> is_c_gpr;
     BitField<20, 24, s64> smem_imm;
-    BitField<0, 5, ControlCode> flow_control_code;
+    BitField<0, 5, ConditionCode> flow_condition_code;
 
     Attribute attribute;
     Sampler sampler;