diff options
Diffstat (limited to 'src/video_core/engines')
| -rw-r--r-- | src/video_core/engines/maxwell_3d.cpp | 6 | ||||
| -rw-r--r-- | src/video_core/engines/maxwell_3d.h | 27 | ||||
| -rw-r--r-- | src/video_core/engines/shader_bytecode.h | 12 |
3 files changed, 29 insertions, 16 deletions
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp index 15a7a9d6a..e1cb8b0b0 100644 --- a/src/video_core/engines/maxwell_3d.cpp +++ b/src/video_core/engines/maxwell_3d.cpp @@ -88,11 +88,11 @@ void Maxwell3D::InitializeRegisterDefaults() { color_mask.A.Assign(1); } - // Commercial games seem to assume this value is enabled and nouveau sets this value manually. + // NVN games expect these values to be enabled at boot + regs.rasterize_enable = 1; regs.rt_separate_frag_data = 1; - - // Some games (like Super Mario Odyssey) assume that SRGB is enabled. regs.framebuffer_srgb = 1; + mme_inline[MAXWELL3D_REG_INDEX(draw.vertex_end_gl)] = true; mme_inline[MAXWELL3D_REG_INDEX(draw.vertex_begin_gl)] = true; mme_inline[MAXWELL3D_REG_INDEX(vertex_buffer.count)] = true; diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h index dbb4e597f..a35e7a195 100644 --- a/src/video_core/engines/maxwell_3d.h +++ b/src/video_core/engines/maxwell_3d.h @@ -657,7 +657,11 @@ public: std::array<f32, 4> tess_level_outer; std::array<f32, 2> tess_level_inner; - INSERT_UNION_PADDING_WORDS(0x102); + INSERT_UNION_PADDING_WORDS(0x10); + + u32 rasterize_enable; + + INSERT_UNION_PADDING_WORDS(0xF1); u32 tfb_enabled; @@ -707,13 +711,15 @@ public: u32 color_mask_common; - INSERT_UNION_PADDING_WORDS(0x6); - - u32 rt_separate_frag_data; + INSERT_UNION_PADDING_WORDS(0x2); f32 depth_bounds[2]; - INSERT_UNION_PADDING_WORDS(0xA); + INSERT_UNION_PADDING_WORDS(0x2); + + u32 rt_separate_frag_data; + + INSERT_UNION_PADDING_WORDS(0xC); struct { u32 address_high; @@ -1030,7 +1036,12 @@ public: BitField<4, 1, u32> depth_clamp_far; } view_volume_clip_control; - INSERT_UNION_PADDING_WORDS(0x21); + INSERT_UNION_PADDING_WORDS(0x1F); + + u32 depth_bounds_enable; + + INSERT_UNION_PADDING_WORDS(1); + struct { u32 enable; LogicOperation operation; @@ -1420,6 +1431,7 @@ ASSERT_REG_POSITION(sync_info, 0xB2); ASSERT_REG_POSITION(tess_mode, 0xC8); ASSERT_REG_POSITION(tess_level_outer, 0xC9); ASSERT_REG_POSITION(tess_level_inner, 0xCD); +ASSERT_REG_POSITION(rasterize_enable, 0xDF); ASSERT_REG_POSITION(tfb_enabled, 0x1D1); ASSERT_REG_POSITION(rt, 0x200); ASSERT_REG_POSITION(viewport_transform, 0x280); @@ -1439,7 +1451,7 @@ ASSERT_REG_POSITION(stencil_back_func_mask, 0x3D6); ASSERT_REG_POSITION(stencil_back_mask, 0x3D7); ASSERT_REG_POSITION(color_mask_common, 0x3E4); ASSERT_REG_POSITION(rt_separate_frag_data, 0x3EB); -ASSERT_REG_POSITION(depth_bounds, 0x3EC); +ASSERT_REG_POSITION(depth_bounds, 0x3E7); ASSERT_REG_POSITION(zeta, 0x3F8); ASSERT_REG_POSITION(clear_flags, 0x43E); ASSERT_REG_POSITION(vertex_attrib_format, 0x458); @@ -1495,6 +1507,7 @@ ASSERT_REG_POSITION(cull, 0x646); ASSERT_REG_POSITION(pixel_center_integer, 0x649); ASSERT_REG_POSITION(viewport_transform_enabled, 0x64B); ASSERT_REG_POSITION(view_volume_clip_control, 0x64F); +ASSERT_REG_POSITION(depth_bounds_enable, 0x66F); ASSERT_REG_POSITION(logic_op, 0x671); ASSERT_REG_POSITION(clear_buffers, 0x674); ASSERT_REG_POSITION(color_mask, 0x680); diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 269ed6127..57b57c647 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h @@ -1239,7 +1239,7 @@ union Instruction { BitField<35, 1, u64> ndv_flag; BitField<49, 1, u64> nodep_flag; BitField<50, 1, u64> dc_flag; - BitField<54, 2, u64> info; + BitField<54, 2, u64> offset_mode; BitField<56, 2, u64> component; bool UsesMiscMode(TextureMiscMode mode) const { @@ -1251,9 +1251,9 @@ union Instruction { case TextureMiscMode::DC: return dc_flag != 0; case TextureMiscMode::AOFFI: - return info == 1; + return offset_mode == 1; case TextureMiscMode::PTP: - return info == 2; + return offset_mode == 2; default: break; } @@ -1265,7 +1265,7 @@ union Instruction { BitField<35, 1, u64> ndv_flag; BitField<49, 1, u64> nodep_flag; BitField<50, 1, u64> dc_flag; - BitField<33, 2, u64> info; + BitField<33, 2, u64> offset_mode; BitField<37, 2, u64> component; bool UsesMiscMode(TextureMiscMode mode) const { @@ -1277,9 +1277,9 @@ union Instruction { case TextureMiscMode::DC: return dc_flag != 0; case TextureMiscMode::AOFFI: - return info == 1; + return offset_mode == 1; case TextureMiscMode::PTP: - return info == 2; + return offset_mode == 2; default: break; } |