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-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp83
-rw-r--r--src/core/hle/service/gsp_gpu.cpp47
2 files changed, 98 insertions, 32 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 5f8826034..9ed61947e 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -36,7 +36,8 @@ enum {
CALL = (1 << 4),
RET = (1 << 5),
END_OF_PAGE = (1 << 6),
- THUMB = (1 << 7)
+ THUMB = (1 << 7),
+ SINGLE_STEP = (1 << 8)
};
#define RM BITS(sht_oper, 0, 3)
@@ -3466,7 +3467,35 @@ enum {
MICROPROFILE_DEFINE(DynCom_Decode, "DynCom", "Decode", MP_RGB(255, 64, 64));
-static int InterpreterTranslate(ARMul_State* cpu, int& bb_start, u32 addr) {
+static unsigned int InterpreterTranslateInstruction(const ARMul_State* cpu, const u32 phys_addr, ARM_INST_PTR& inst_base) {
+ unsigned int inst_size = 4;
+ unsigned int inst = Memory::Read32(phys_addr & 0xFFFFFFFC);
+
+ // If we are in Thumb mode, we'll translate one Thumb instruction to the corresponding ARM instruction
+ if (cpu->TFlag) {
+ u32 arm_inst;
+ ThumbDecodeStatus state = DecodeThumbInstruction(inst, phys_addr, &arm_inst, &inst_size, &inst_base);
+
+ // We have translated the Thumb branch instruction in the Thumb decoder
+ if (state == ThumbDecodeStatus::BRANCH) {
+ return inst_size;
+ }
+ inst = arm_inst;
+ }
+
+ int idx;
+ if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) {
+ std::string disasm = ARM_Disasm::Disassemble(phys_addr, inst);
+ LOG_ERROR(Core_ARM11, "Decode failure.\tPC : [0x%x]\tInstruction : %s [%x]", phys_addr, disasm.c_str(), inst);
+ LOG_ERROR(Core_ARM11, "cpsr=0x%x, cpu->TFlag=%d, r15=0x%x", cpu->Cpsr, cpu->TFlag, cpu->Reg[15]);
+ CITRA_IGNORE_EXIT(-1);
+ }
+ inst_base = arm_instruction_trans[idx](inst, idx);
+
+ return inst_size;
+}
+
+static int InterpreterTranslateBlock(ARMul_State* cpu, int& bb_start, u32 addr) {
Common::Profiling::ScopeTimer timer_decode(profile_decode);
MICROPROFILE_SCOPE(DynCom_Decode);
@@ -3475,8 +3504,6 @@ static int InterpreterTranslate(ARMul_State* cpu, int& bb_start, u32 addr) {
// Go on next, until terminal instruction
// Save start addr of basicblock in CreamCache
ARM_INST_PTR inst_base = nullptr;
- unsigned int inst, inst_size = 4;
- int idx;
int ret = NON_BRANCH;
int size = 0; // instruction size of basic block
bb_start = top;
@@ -3485,30 +3512,10 @@ static int InterpreterTranslate(ARMul_State* cpu, int& bb_start, u32 addr) {
u32 pc_start = cpu->Reg[15];
while (ret == NON_BRANCH) {
- inst = Memory::Read32(phys_addr & 0xFFFFFFFC);
+ unsigned int inst_size = InterpreterTranslateInstruction(cpu, phys_addr, inst_base);
size++;
- // If we are in Thumb mode, we'll translate one Thumb instruction to the corresponding ARM instruction
- if (cpu->TFlag) {
- u32 arm_inst;
- ThumbDecodeStatus state = DecodeThumbInstruction(inst, phys_addr, &arm_inst, &inst_size, &inst_base);
-
- // We have translated the Thumb branch instruction in the Thumb decoder
- if (state == ThumbDecodeStatus::BRANCH) {
- goto translated;
- }
- inst = arm_inst;
- }
-
- if (DecodeARMInstruction(inst, &idx) == ARMDecodeStatus::FAILURE) {
- std::string disasm = ARM_Disasm::Disassemble(phys_addr, inst);
- LOG_ERROR(Core_ARM11, "Decode failure.\tPC : [0x%x]\tInstruction : %s [%x]", phys_addr, disasm.c_str(), inst);
- LOG_ERROR(Core_ARM11, "cpsr=0x%x, cpu->TFlag=%d, r15=0x%x", cpu->Cpsr, cpu->TFlag, cpu->Reg[15]);
- CITRA_IGNORE_EXIT(-1);
- }
- inst_base = arm_instruction_trans[idx](inst, idx);
-translated:
phys_addr += inst_size;
if ((phys_addr & 0xfff) == 0) {
@@ -3522,6 +3529,27 @@ translated:
return KEEP_GOING;
}
+static int InterpreterTranslateSingle(ARMul_State* cpu, int& bb_start, u32 addr) {
+ Common::Profiling::ScopeTimer timer_decode(profile_decode);
+ MICROPROFILE_SCOPE(DynCom_Decode);
+
+ ARM_INST_PTR inst_base = nullptr;
+ bb_start = top;
+
+ u32 phys_addr = addr;
+ u32 pc_start = cpu->Reg[15];
+
+ InterpreterTranslateInstruction(cpu, phys_addr, inst_base);
+
+ if (inst_base->br == NON_BRANCH) {
+ inst_base->br = SINGLE_STEP;
+ }
+
+ cpu->instruction_cache[pc_start] = bb_start;
+
+ return KEEP_GOING;
+}
+
static int clz(unsigned int x) {
int n;
if (x == 0) return (32);
@@ -3871,8 +3899,11 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
auto itr = cpu->instruction_cache.find(cpu->Reg[15]);
if (itr != cpu->instruction_cache.end()) {
ptr = itr->second;
+ } else if (cpu->NumInstrsToExecute != 1) {
+ if (InterpreterTranslateBlock(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION)
+ goto END;
} else {
- if (InterpreterTranslate(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION)
+ if (InterpreterTranslateSingle(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION)
goto END;
}
diff --git a/src/core/hle/service/gsp_gpu.cpp b/src/core/hle/service/gsp_gpu.cpp
index 16f2175ac..0c655395e 100644
--- a/src/core/hle/service/gsp_gpu.cpp
+++ b/src/core/hle/service/gsp_gpu.cpp
@@ -302,6 +302,22 @@ static void FlushDataCache(Service::Interface* self) {
}
/**
+ * GSP_GPU::SetAxiConfigQoSMode service function
+ * Inputs:
+ * 1 : Mode, unused in emulator
+ * Outputs:
+ * 1 : Result of function, 0 on success, otherwise error code
+ */
+static void SetAxiConfigQoSMode(Service::Interface* self) {
+ u32* cmd_buff = Kernel::GetCommandBuffer();
+ u32 mode = cmd_buff[1];
+
+ cmd_buff[1] = RESULT_SUCCESS.raw; // No error
+
+ LOG_WARNING(Service_GSP, "(STUBBED) called mode=0x%08X", mode);
+}
+
+/**
* GSP_GPU::RegisterInterruptRelayQueue service function
* Inputs:
* 1 : "Flags" field, purpose is unknown
@@ -318,6 +334,12 @@ static void RegisterInterruptRelayQueue(Service::Interface* self) {
g_interrupt_event = Kernel::g_handle_table.Get<Kernel::Event>(cmd_buff[3]);
ASSERT_MSG((g_interrupt_event != nullptr), "handle is not valid!");
+ g_interrupt_event->name = "GSP_GPU::interrupt_event";
+
+ using Kernel::MemoryPermission;
+ g_shared_memory = Kernel::SharedMemory::Create(0x1000, MemoryPermission::ReadWrite,
+ MemoryPermission::ReadWrite, "GSPSharedMem");
+
Handle shmem_handle = Kernel::g_handle_table.Create(g_shared_memory).MoveFrom();
// This specific code is required for a successful initialization, rather than 0
@@ -330,6 +352,22 @@ static void RegisterInterruptRelayQueue(Service::Interface* self) {
}
/**
+ * GSP_GPU::UnregisterInterruptRelayQueue service function
+ * Outputs:
+ * 1 : Result of function, 0 on success, otherwise error code
+ */
+static void UnregisterInterruptRelayQueue(Service::Interface* self) {
+ u32* cmd_buff = Kernel::GetCommandBuffer();
+
+ g_shared_memory = nullptr;
+ g_interrupt_event = nullptr;
+
+ cmd_buff[1] = RESULT_SUCCESS.raw;
+
+ LOG_WARNING(Service_GSP, "called");
+}
+
+/**
* Signals that the specified interrupt type has occurred to userland code
* @param interrupt_id ID of interrupt that is being signalled
* @todo This should probably take a thread_id parameter and only signal this thread?
@@ -607,11 +645,11 @@ const Interface::FunctionInfo FunctionTable[] = {
{0x000D0140, nullptr, "SetDisplayTransfer"},
{0x000E0180, nullptr, "SetTextureCopy"},
{0x000F0200, nullptr, "SetMemoryFill"},
- {0x00100040, nullptr, "SetAxiConfigQoSMode"},
+ {0x00100040, SetAxiConfigQoSMode, "SetAxiConfigQoSMode"},
{0x00110040, nullptr, "SetPerfLogMode"},
{0x00120000, nullptr, "GetPerfLog"},
{0x00130042, RegisterInterruptRelayQueue, "RegisterInterruptRelayQueue"},
- {0x00140000, nullptr, "UnregisterInterruptRelayQueue"},
+ {0x00140000, UnregisterInterruptRelayQueue, "UnregisterInterruptRelayQueue"},
{0x00150002, nullptr, "TryAcquireRight"},
{0x00160042, nullptr, "AcquireRight"},
{0x00170000, nullptr, "ReleaseRight"},
@@ -632,10 +670,7 @@ Interface::Interface() {
Register(FunctionTable);
g_interrupt_event = nullptr;
-
- using Kernel::MemoryPermission;
- g_shared_memory = Kernel::SharedMemory::Create(0x1000, MemoryPermission::ReadWrite,
- MemoryPermission::ReadWrite, "GSPSharedMem");
+ g_shared_memory = nullptr;
g_thread_id = 0;
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-20 03:19:16 +0200