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-rw-r--r--src/core/arm/skyeye_common/vfp/vfp.cpp20
-rw-r--r--src/core/arm/skyeye_common/vfp/vfp.h1
-rw-r--r--src/core/arm/skyeye_common/vfp/vfpinstr.cpp35
3 files changed, 44 insertions, 12 deletions
diff --git a/src/core/arm/skyeye_common/vfp/vfp.cpp b/src/core/arm/skyeye_common/vfp/vfp.cpp
index 5c036caeb..10d640f37 100644
--- a/src/core/arm/skyeye_common/vfp/vfp.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfp.cpp
@@ -141,7 +141,7 @@ unsigned VFPMRRC(ARMul_State* state, unsigned type, u32 instr, u32* value1, u32*
{
if (CoProc == 10 && (OPC_1 & 0xD) == 1)
{
- VFP_DEBUG_UNIMPLEMENTED(VMOVBRRSS);
+ VMOVBRRSS(state, BIT(20), Rt, Rt2, BIT(5)<<4|CRm, value1, value2);
return ARMul_DONE;
}
@@ -175,7 +175,7 @@ unsigned VFPMCRR(ARMul_State* state, unsigned type, u32 instr, u32 value1, u32 v
{
if (CoProc == 10 && (OPC_1 & 0xD) == 1)
{
- VFP_DEBUG_UNIMPLEMENTED(VMOVBRRSS);
+ VMOVBRRSS(state, BIT(20), Rt, Rt2, BIT(5)<<4|CRm, &value1, &value2);
return ARMul_DONE;
}
@@ -504,6 +504,22 @@ void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword
state->ExtReg[n*2] = *value1;
}
}
+void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2)
+{
+ DBG("VMOV(BRRSS) :\n");
+ if (to_arm)
+ {
+ DBG("\tr[%d-%d] <= s[%d-%d]=[%x-%x]\n", t2, t, n+1, n, state->ExtReg[n+1], state->ExtReg[n]);
+ *value1 = state->ExtReg[n+0];
+ *value2 = state->ExtReg[n+1];
+ }
+ else
+ {
+ DBG("\ts[%d-%d] <= r[%d-%d]=[%x-%x]\n", n+1, n, t2, t, *value2, *value1);
+ state->ExtReg[n+0] = *value1;
+ state->ExtReg[n+1] = *value2;
+ }
+}
/* ----------- MCR ------------ */
void VMSR(ARMul_State* state, ARMword reg, ARMword Rt)
diff --git a/src/core/arm/skyeye_common/vfp/vfp.h b/src/core/arm/skyeye_common/vfp/vfp.h
index f9e8d521d..539fb0131 100644
--- a/src/core/arm/skyeye_common/vfp/vfp.h
+++ b/src/core/arm/skyeye_common/vfp/vfp.h
@@ -97,6 +97,7 @@ u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr);
void VMRS(ARMul_State * state, ARMword reg, ARMword Rt, ARMword *value);
void VMOVBRS(ARMul_State * state, ARMword to_arm, ARMword t, ARMword n, ARMword *value);
void VMOVBRRD(ARMul_State * state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword *value1, ARMword *value2);
+void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2);
void VMOVI(ARMul_State * state, ARMword single, ARMword d, ARMword imm);
void VMOVR(ARMul_State * state, ARMword single, ARMword d, ARMword imm);
/* MCR */
diff --git a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
index 27dc8a008..cc70fc33c 100644
--- a/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
+++ b/src/core/arm/skyeye_common/vfp/vfpinstr.cpp
@@ -2702,7 +2702,7 @@ ARM_INST_PTR INTERPRETER_TRANSLATE(vmovbrrss)(unsigned int inst, int index)
inst_cream->t = BITS(inst, 12, 15);
inst_cream->t2 = BITS(inst, 16, 19);
inst_cream->m = BITS(inst, 0, 3)<<1|BIT(inst, 5);
-
+
return inst_base;
}
#endif
@@ -2711,10 +2711,11 @@ VMOVBRRSS_INST:
{
if ((inst_base->cond == 0xe) || CondPassed(cpu, inst_base->cond)) {
CHECK_VFP_ENABLED;
-
- vmovbrrss_inst *inst_cream = (vmovbrrss_inst *)inst_base->component;
-
- VFP_DEBUG_UNIMPLEMENTED(VMOVBRRSS);
+
+ vmovbrrss_inst* const inst_cream = (vmovbrrss_inst*)inst_base->component;
+
+ VMOVBRRSS(cpu, inst_cream->to_arm, inst_cream->t, inst_cream->t2, inst_cream->m,
+ &cpu->Reg[inst_cream->t], &cpu->Reg[inst_cream->t2]);
}
cpu->Reg[15] += GET_INST_SIZE(cpu);
INC_PC(sizeof(vmovbrrss_inst));
@@ -2729,15 +2730,29 @@ DYNCOM_FILL_ACTION(vmovbrrss),
int DYNCOM_TAG(vmovbrrss)(cpu_t *cpu, addr_t pc, uint32_t instr, tag_t *tag, addr_t *new_pc, addr_t *next_pc)
{
int instr_size = INSTR_SIZE;
- DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
- arm_tag_trap(cpu, pc, instr, tag, new_pc, next_pc);
+
+ arm_tag_continue(cpu, pc, instr, tag, new_pc, next_pc);
+ if (instr >> 28 != 0xE)
+ *tag |= TAG_CONDITIONAL;
+
return instr_size;
}
#endif
#ifdef VFP_DYNCOM_TRANS
-int DYNCOM_TRANS(vmovbrrss)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc){
- DBG("\t\tin %s instruction is not implemented.\n", __FUNCTION__);
- arch_arm_undef(cpu, bb, instr);
+int DYNCOM_TRANS(vmovbrrss)(cpu_t *cpu, uint32_t instr, BasicBlock *bb, addr_t pc)
+{
+ int to_arm = BIT(20) == 1;
+ int t = BITS(12, 15);
+ int t2 = BITS(16, 19);
+ int n = BIT(5)<<4 | BITS(0, 3);
+ if (to_arm) {
+ LET(t, IBITCAST32(FR32(n + 0)));
+ LET(t2, IBITCAST32(FR32(n + 1)));
+ }
+ else {
+ LETFPS(n + 0, FPBITCAST32(R(t)));
+ LETFPS(n + 1, FPBITCAST32(R(t2)));
+ }
return No_exp;
}
#endif