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authorSubv <subv2112@gmail.com>2018-04-19 20:34:50 +0200
committerSubv <subv2112@gmail.com>2018-04-19 20:46:32 +0200
commitfe8484213759330ef8c7cf2eda8130c8e3a11198 (patch)
treef356e88c666239441773affcbdea0babdd40f180 /src/video_core/renderer_opengl/gl_shader_decompiler.cpp
parentShaderGen: Fixed a case where the TEXS instruction would use the same registers for the input and the output. (diff)
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Diffstat (limited to '')
-rw-r--r--src/video_core/renderer_opengl/gl_shader_decompiler.cpp22
1 files changed, 16 insertions, 6 deletions
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
index b18f25026..4cc617c97 100644
--- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
+++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
@@ -190,9 +190,14 @@ private:
}
}
- /// Generates code representing an immediate value
- static std::string GetImmediate(const Instruction& instr) {
- return std::to_string(instr.alu.GetImm20());
+ /// Generates code representing a 19-bit immediate value
+ static std::string GetImmediate19(const Instruction& instr) {
+ return std::to_string(instr.alu.GetImm20_19());
+ }
+
+ /// Generates code representing a 32-bit immediate value
+ static std::string GetImmediate32(const Instruction& instr) {
+ return std::to_string(instr.alu.GetImm20_32());
}
/// Generates code representing a temporary (GPR) register.
@@ -276,7 +281,7 @@ private:
std::string op_b = instr.alu.negate_b ? "-" : "";
if (instr.is_b_imm) {
- op_b += GetImmediate(instr);
+ op_b += GetImmediate19(instr);
} else {
if (instr.is_b_gpr) {
op_b += GetRegister(instr.gpr20);
@@ -296,6 +301,11 @@ private:
SetDest(0, dest, op_a + " * " + op_b, 1, 1, instr.alu.abs_d);
break;
}
+ case OpCode::Id::FMUL32_IMM: {
+ // fmul32i doesn't have abs or neg bits.
+ SetDest(0, dest, GetRegister(instr.gpr8) + " * " + GetImmediate32(instr), 1, 1);
+ break;
+ }
case OpCode::Id::FADD_C:
case OpCode::Id::FADD_R:
case OpCode::Id::FADD_IMM: {
@@ -364,7 +374,7 @@ private:
break;
}
case OpCode::Id::FFMA_IMM: {
- op_b += GetImmediate(instr);
+ op_b += GetImmediate19(instr);
op_c += GetRegister(instr.gpr39);
break;
}
@@ -593,7 +603,7 @@ private:
std::set<Attribute::Index> declr_input_attribute;
std::set<Attribute::Index> declr_output_attribute;
std::array<ConstBufferEntry, Maxwell3D::Regs::MaxConstBuffers> declr_const_buffers;
-};
+}; // namespace Decompiler
std::string GetCommonDeclarations() {
return "bool exec_shader();";