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| author | Subv <subv2112@gmail.com> | 2018-06-19 02:50:35 +0200 |
|---|---|---|
| committer | Subv <subv2112@gmail.com> | 2018-06-19 02:50:35 +0200 |
| commit | eab7457c00e4ab21ea2533441de03ff9cdda5ff3 (patch) | |
| tree | f187d57807adbca8cbf87f3d2fe9915f06b09224 /src/video_core/renderer_opengl/gl_shader_decompiler.cpp | |
| parent | Merge pull request #570 from bunnei/astc (diff) | |
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Diffstat (limited to '')
| -rw-r--r-- | src/video_core/renderer_opengl/gl_shader_decompiler.cpp | 27 |
1 files changed, 15 insertions, 12 deletions
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp index 6ec0a0742..6dc695def 100644 --- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp +++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp @@ -852,11 +852,6 @@ private: break; } - case OpCode::Id::MOV32_IMM: { - // mov32i doesn't have abs or neg bits. - regs.SetRegisterToFloat(instr.gpr0, 0, GetImmediate32(instr), 1, 1); - break; - } case OpCode::Id::FMUL_C: case OpCode::Id::FMUL_R: case OpCode::Id::FMUL_IMM: { @@ -864,13 +859,6 @@ private: instr.alu.saturate_d); break; } - case OpCode::Id::FMUL32_IMM: { - // fmul32i doesn't have abs or neg bits. - regs.SetRegisterToFloat( - instr.gpr0, 0, - regs.GetRegisterAsFloat(instr.gpr8) + " * " + GetImmediate32(instr), 1, 1); - break; - } case OpCode::Id::FADD_C: case OpCode::Id::FADD_R: case OpCode::Id::FADD_IMM: { @@ -943,6 +931,21 @@ private: } break; } + case OpCode::Type::ArithmeticImmediate: { + switch (opcode->GetId()) { + case OpCode::Id::MOV32_IMM: { + regs.SetRegisterToFloat(instr.gpr0, 0, GetImmediate32(instr), 1, 1); + break; + } + case OpCode::Id::FMUL32_IMM: { + regs.SetRegisterToFloat( + instr.gpr0, 0, + regs.GetRegisterAsFloat(instr.gpr8) + " * " + GetImmediate32(instr), 1, 1); + break; + } + } + break; + } case OpCode::Type::Bfe: { ASSERT_MSG(!instr.bfe.negate_b, "Unimplemented"); |