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author | wwylele <wwylele@gmail.com> | 2017-08-03 00:40:42 +0200 |
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committer | wwylele <wwylele@gmail.com> | 2017-08-07 09:30:05 +0200 |
commit | baa24f4ea9d9c4d7c1bd60ba8a6fc188dfa9cc8f (patch) | |
tree | fb4aff72d838100708e45cc022287af349d245e6 /src/video_core/regs_pipeline.h | |
parent | Merge pull request #2848 from wwylele/shader-loop-fix (diff) | |
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Diffstat (limited to '')
-rw-r--r-- | src/video_core/regs_pipeline.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/video_core/regs_pipeline.h b/src/video_core/regs_pipeline.h index 31c747d77..8b6369297 100644 --- a/src/video_core/regs_pipeline.h +++ b/src/video_core/regs_pipeline.h @@ -202,7 +202,14 @@ struct PipelineRegs { /// Number of input attributes to the vertex shader minus 1 BitField<0, 4, u32> max_input_attrib_index; - INSERT_PADDING_WORDS(2); + INSERT_PADDING_WORDS(1); + + // The shader unit 3, which can be used for both vertex and geometry shader, gets its + // configuration depending on this register. If this is not set, unit 3 will share some + // configuration with other units. It is known that program code and swizzle pattern uploaded + // via regs.vs will be also uploaded to unit 3 if this is not set. Although very likely, it is + // still unclear whether uniforms and other configuration can be also shared. + BitField<0, 1, u32> gs_unit_exclusive_configuration; enum class GPUMode : u32 { Drawing = 0, |