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author | Subv <subv2112@gmail.com> | 2018-08-18 21:36:37 +0200 |
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committer | Subv <subv2112@gmail.com> | 2018-08-18 21:36:37 +0200 |
commit | 8335b2f115d8c2e082f1b085eedb54d334489f6d (patch) | |
tree | 108bfacaaa4d40d36a0e0aa41701d7330ded4ee6 /src/video_core/engines | |
parent | Merge pull request #1100 from ogniK5377/missing-pred (diff) | |
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Diffstat (limited to '')
-rw-r--r-- | src/video_core/engines/shader_bytecode.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index b038a9d92..6cfb9c5f8 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h @@ -214,6 +214,11 @@ enum class FlowCondition : u64 { Fcsm_Tr = 0x1C, // TODO(bunnei): What is this used for? }; +enum class PredicateResultMode : u64 { + None = 0x0, + NotZero = 0x3, +}; + union Instruction { Instruction& operator=(const Instruction& instr) { value = instr.value; @@ -254,7 +259,7 @@ union Instruction { BitField<39, 1, u64> invert_a; BitField<40, 1, u64> invert_b; BitField<41, 2, LogicOperation> operation; - BitField<44, 2, u64> unk44; + BitField<44, 2, PredicateResultMode> pred_result_mode; BitField<48, 3, Pred> pred48; } lop; |