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author | Subv <subv2112@gmail.com> | 2018-03-19 22:49:41 +0100 |
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committer | Subv <subv2112@gmail.com> | 2018-03-19 22:55:33 +0100 |
commit | 7a27a117706d413af0b677f42d16374b0cb2f82b (patch) | |
tree | efb71f3b74882124c4277f3b83acb86e702c02ff /src/video_core/engines/maxwell_3d.h | |
parent | GPU: Added the render target (RT) registers to Maxwell3D's reg structure. (diff) | |
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Diffstat (limited to '')
-rw-r--r-- | src/video_core/engines/maxwell_3d.h | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h index f354241e4..c2db3154a 100644 --- a/src/video_core/engines/maxwell_3d.h +++ b/src/video_core/engines/maxwell_3d.h @@ -83,7 +83,22 @@ public: } } rt[NumRenderTargets]; - INSERT_PADDING_WORDS(0x207); + INSERT_PADDING_WORDS(0x178); + + struct { + u32 address_high; + u32 address_low; + u32 format; + u32 block_dimensions; + u32 layer_stride; + + GPUVAddr Address() const { + return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) | + address_low); + } + } zeta; + + INSERT_PADDING_WORDS(0x8A); struct { union { @@ -321,6 +336,7 @@ private: "Field " #field_name " has invalid position") ASSERT_REG_POSITION(rt, 0x200); +ASSERT_REG_POSITION(zeta, 0x3F8); ASSERT_REG_POSITION(rt_control, 0x487); ASSERT_REG_POSITION(tsc, 0x557); ASSERT_REG_POSITION(tic, 0x55D); |