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authorReinUsesLisp <reinuseslisp@airmail.cc>2021-03-27 07:08:31 +0100
committerameerj <52414509+ameerj@users.noreply.github.com>2021-07-23 03:51:24 +0200
commit675a82416d7775dc7a252a5d8f5b704e6b8f2326 (patch)
tree4964c92716029716255d75e26dcc033487df6b1e /src/shader_recompiler/frontend/maxwell
parentvk_pipeline_cache: Fix pipeline and shader caches (diff)
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Diffstat (limited to 'src/shader_recompiler/frontend/maxwell')
-rw-r--r--src/shader_recompiler/frontend/maxwell/program.cpp3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/program.cpp b/src/shader_recompiler/frontend/maxwell/program.cpp
index 0074eb89b..6efaf6ee0 100644
--- a/src/shader_recompiler/frontend/maxwell/program.cpp
+++ b/src/shader_recompiler/frontend/maxwell/program.cpp
@@ -33,6 +33,9 @@ IR::Program TranslateProgram(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Blo
program.blocks = VisitAST(inst_pool, block_pool, env, cfg);
program.post_order_blocks = PostOrder(program.blocks);
program.stage = env.ShaderStage();
+ if (program.stage == Stage::Compute) {
+ program.workgroup_size = env.WorkgroupSize();
+ }
RemoveUnreachableBlocks(program);
// Replace instructions before the SSA rewrite