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author | archshift <admin@archshift.com> | 2015-03-06 04:38:23 +0100 |
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committer | archshift <admin@archshift.com> | 2015-03-06 04:38:23 +0100 |
commit | 47010fea3126bfe0b675810ea9471a25191d548f (patch) | |
tree | 73c3d747aeba48f0ac66d6c6783ae0867e4b55c3 /src/core/hle/service/gsp_gpu.cpp | |
parent | Merge pull request #615 from Subv/services (diff) | |
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Diffstat (limited to '')
-rw-r--r-- | src/core/hle/service/gsp_gpu.cpp | 44 |
1 files changed, 39 insertions, 5 deletions
diff --git a/src/core/hle/service/gsp_gpu.cpp b/src/core/hle/service/gsp_gpu.cpp index c23cfa3c8..3b4a7b664 100644 --- a/src/core/hle/service/gsp_gpu.cpp +++ b/src/core/hle/service/gsp_gpu.cpp @@ -7,7 +7,9 @@ #include "core/mem_map.h" #include "core/hle/kernel/event.h" #include "core/hle/kernel/shared_memory.h" +#include "core/hle/result.h" #include "gsp_gpu.h" +#include "core/hw/hw.h" #include "core/hw/gpu.h" #include "video_core/gpu_debugger.h" @@ -85,7 +87,7 @@ static void WriteHWRegs(u32 base_address, u32 size_in_bytes, const u32* data) { return; while (size_in_bytes > 0) { - GPU::Write<u32>(base_address + 0x1EB00000, *data); + HW::Write<u32>(base_address + 0x1EB00000, *data); size_in_bytes -= 4; ++data; @@ -131,12 +133,12 @@ static void WriteHWRegsWithMask(u32 base_address, u32 size_in_bytes, const u32* const u32 reg_address = base_address + 0x1EB00000; u32 reg_value; - GPU::Read<u32>(reg_value, reg_address); + HW::Read<u32>(reg_value, reg_address); // Update the current value of the register only for set mask bits reg_value = (reg_value & ~*masks) | (*data | *masks); - GPU::Write<u32>(reg_address, reg_value); + HW::Write<u32>(reg_address, reg_value); size_in_bytes -= 4; ++data; @@ -188,7 +190,7 @@ static void ReadHWRegs(Service::Interface* self) { u32* dst = (u32*)Memory::GetPointer(cmd_buff[0x41]); while (size > 0) { - GPU::Read<u32>(*dst, reg_addr + 0x1EB00000); + HW::Read<u32>(*dst, reg_addr + 0x1EB00000); size -= 4; ++dst; @@ -427,6 +429,38 @@ static void ExecuteCommand(const Command& command, u32 thread_id) { } } +/** + * GSP_GPU::SetLcdForceBlack service function + * + * Enable or disable REG_LCDCOLORFILL with the color black. + * + * Inputs: + * 1: Black color fill flag (0 = don't fill, !0 = fill) + * Outputs: + * 1: Result code + */ +void SetLcdForceBlack(Service::Interface* self) { + // TODO: currently has no effect, as LCD reg writes have nowhere to go. + + u32* cmd_buff = Kernel::GetCommandBuffer(); + bool enable_black = cmd_buff[1] != 0; + u32 data = 0; + + if (enable_black) { + // Sets bit 24 to 1, enabling the fill + // Since data is already 0x00000000, there is no need to explicitly set + // bits 0-23 to zero (black), or bit 24 to 0 (fill disabled). + data |= (1 << 24); + } + + u32 data_main = data; + u32 data_sub = data; + WriteHWRegs(0x202204, 4, &data_main); // Main LCD + WriteHWRegs(0x202A04, 4, &data_sub); // Sub LCD + + cmd_buff[1] = RESULT_SUCCESS.raw; +} + /// This triggers handling of the GX command written to the command buffer in shared memory. static void TriggerCmdReqQueue(Service::Interface* self) { // Iterate through each thread's command queue... @@ -460,7 +494,7 @@ const Interface::FunctionInfo FunctionTable[] = { {0x00080082, FlushDataCache, "FlushDataCache"}, {0x00090082, nullptr, "InvalidateDataCache"}, {0x000A0044, nullptr, "RegisterInterruptEvents"}, - {0x000B0040, nullptr, "SetLcdForceBlack"}, + {0x000B0040, SetLcdForceBlack, "SetLcdForceBlack"}, {0x000C0000, TriggerCmdReqQueue, "TriggerCmdReqQueue"}, {0x000D0140, nullptr, "SetDisplayTransfer"}, {0x000E0180, nullptr, "SetTextureCopy"}, |