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author | Lioncash <mathew1800@gmail.com> | 2015-01-08 17:00:04 +0100 |
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committer | Lioncash <mathew1800@gmail.com> | 2015-01-08 17:09:21 +0100 |
commit | 1cef6e92d5e2b66aa7b01fd6f7ec0e9be6515446 (patch) | |
tree | b50a9ac668b56887d2c6931e8f0fa07d57c699bd /src/core/arm/dyncom/arm_dyncom_interpreter.cpp | |
parent | Merge pull request #442 from lioncash/smul (diff) | |
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Diffstat (limited to '')
-rw-r--r-- | src/core/arm/dyncom/arm_dyncom_interpreter.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp index 7c710ccde..e3ca02e98 100644 --- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp +++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp @@ -6696,10 +6696,10 @@ unsigned InterpreterMainLoop(ARMul_State* state) { { if (inst_base->cond == 0xE || CondPassed(cpu, inst_base->cond)) { umaal_inst* const inst_cream = (umaal_inst*)inst_base->component; - const u32 rm = RM; - const u32 rn = RN; - const u32 rd_lo = RDLO; - const u32 rd_hi = RDHI; + const u64 rm = RM; + const u64 rn = RN; + const u64 rd_lo = RDLO; + const u64 rd_hi = RDHI; const u64 result = (rm * rn) + rd_lo + rd_hi; RDLO = (result & 0xFFFFFFFF); |