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author | aroulin <andy.roulin@epfl.ch> | 2015-08-05 12:12:24 +0200 |
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committer | aroulin <andy.roulin@epfl.ch> | 2015-08-06 15:25:08 +0200 |
commit | 5d81a2fd48cdd3138698beb1da56fa7064f6c5c5 (patch) | |
tree | 808a97ca2ba4d05f1d850cacfaa368e898649036 /src/core/arm/disassembler/arm_disasm.h | |
parent | Merge pull request #1018 from bbarenblat/master (diff) | |
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Diffstat (limited to '')
-rw-r--r-- | src/core/arm/disassembler/arm_disasm.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/core/arm/disassembler/arm_disasm.h b/src/core/arm/disassembler/arm_disasm.h index f94bd4669..a4e4adf2f 100644 --- a/src/core/arm/disassembler/arm_disasm.h +++ b/src/core/arm/disassembler/arm_disasm.h @@ -41,11 +41,13 @@ enum Opcode { OP_MSR, OP_MUL, OP_MVN, + OP_NOP, OP_ORR, OP_PLD, OP_RSB, OP_RSC, OP_SBC, + OP_SEV, OP_SMLAL, OP_SMULL, OP_STC, @@ -63,6 +65,9 @@ enum Opcode { OP_TST, OP_UMLAL, OP_UMULL, + OP_WFE, + OP_WFI, + OP_YIELD, // Define thumb opcodes OP_THUMB_UNDEFINED, @@ -118,6 +123,7 @@ class ARM_Disasm { static Opcode Decode10(uint32_t insn); static Opcode Decode11(uint32_t insn); static Opcode DecodeMUL(uint32_t insn); + static Opcode DecodeMSRImmAndHints(uint32_t insn); static Opcode DecodeLDRH(uint32_t insn); static Opcode DecodeALU(uint32_t insn); @@ -135,6 +141,7 @@ class ARM_Disasm { static std::string DisassembleMUL(Opcode opcode, uint32_t insn); static std::string DisassembleMRS(uint32_t insn); static std::string DisassembleMSR(uint32_t insn); + static std::string DisassembleNoOperands(Opcode opcode, uint32_t insn); static std::string DisassemblePLD(uint32_t insn); static std::string DisassembleSWI(uint32_t insn); static std::string DisassembleSWP(Opcode opcode, uint32_t insn); |