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author | aroulin <andy.roulin@epfl.ch> | 2015-08-06 13:55:56 +0200 |
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committer | aroulin <andy.roulin@epfl.ch> | 2015-08-06 15:50:54 +0200 |
commit | 3425cfe54a46512a2ef35e5254c2d32e14ace69a (patch) | |
tree | da545082e7f2c2e158f56f504ffa35e1fc986a48 /src/core/arm/disassembler/arm_disasm.h | |
parent | Disassembler: ARMv6K hint instructions (diff) | |
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Diffstat (limited to '')
-rw-r--r-- | src/core/arm/disassembler/arm_disasm.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/core/arm/disassembler/arm_disasm.h b/src/core/arm/disassembler/arm_disasm.h index a4e4adf2f..d04fd21eb 100644 --- a/src/core/arm/disassembler/arm_disasm.h +++ b/src/core/arm/disassembler/arm_disasm.h @@ -20,6 +20,7 @@ enum Opcode { OP_BLX, OP_BX, OP_CDP, + OP_CLREX, OP_CLZ, OP_CMN, OP_CMP, @@ -29,6 +30,10 @@ enum Opcode { OP_LDR, OP_LDRB, OP_LDRBT, + OP_LDREX, + OP_LDREXB, + OP_LDREXD, + OP_LDREXH, OP_LDRH, OP_LDRSB, OP_LDRSH, @@ -55,6 +60,10 @@ enum Opcode { OP_STR, OP_STRB, OP_STRBT, + OP_STREX, + OP_STREXB, + OP_STREXD, + OP_STREXH, OP_STRH, OP_STRT, OP_SUB, @@ -122,6 +131,7 @@ class ARM_Disasm { static Opcode Decode01(uint32_t insn); static Opcode Decode10(uint32_t insn); static Opcode Decode11(uint32_t insn); + static Opcode DecodeSyncPrimitive(uint32_t insn); static Opcode DecodeMUL(uint32_t insn); static Opcode DecodeMSRImmAndHints(uint32_t insn); static Opcode DecodeLDRH(uint32_t insn); @@ -143,6 +153,7 @@ class ARM_Disasm { static std::string DisassembleMSR(uint32_t insn); static std::string DisassembleNoOperands(Opcode opcode, uint32_t insn); static std::string DisassemblePLD(uint32_t insn); + static std::string DisassembleREX(Opcode opcode, uint32_t insn); static std::string DisassembleSWI(uint32_t insn); static std::string DisassembleSWP(Opcode opcode, uint32_t insn); }; |